A21 Keyboard Control; A22 Display Control - HP 4262A Operating And Service Manual

Model 4262A
The Nanoprocessor is synchronized with the
1.27MHz Clock and calculates the measured
quantity as a number counted toward the
31.83kHz (100k/7Hz) secondary clock pulse. To
identify which, if any, option is installed and being
used in the instrument, the Nanoprocessor accesses
the option code from the option selection switch
setting when the Data Bus Driver/Receiver is set to
driver mode by a DSR signal. The Nanoprocessor
controls the option section in accord with the
nanoprocessor programs as appropriate to the
selected option.
8-31. A21 KEYBOARD CONTROL.
The A21 Keyboard Control is composed of two
major sections: one is the interrupt control consist-
ing of .the Interrupt Priority Encoder (U24), Multi-
plexer (Ul12 & U23), Row Scan Counter (U2),
Gate (U1) and Flip-Flops (U3 & Ul4); the otheris
the Annunciator Register (U7, U8, Ulb through
U21) which stores and transfers manifold annun-
ciation data (keyboard pushbutton indication,
range indication, circuit mode indication, etc.).
The Row Scan Counter outputs periodic ROW
signals (3 bit) to A2 board as driven by 31.83kHz
secondary clock. These ROW signals are decoded
to the keyboard scan signals which cause, in turn,
specific groups of keys to become valid. Each
group of control keys is enabled, in sequence, to
perform its function. When a keyboard pushbutton
is pressed, the output logic of Ul goes high and
subsequently the Row Scan Counter stops. The
contents of the ROW Scan Counter and the
column number given by CLM @ through CLM 3
signals are coordinated with the address of the key
depressed. Simultaneously, Ul activates Flip-Flops
U3 and U14 causing the INT & signal to be out-
putted. The Interrupt Priority Encoder converts its
INT & through INT 3 input signals into the vector
address signals (4 bit octal code) as appropriate for
nanoprocessor input. INT 1, 2, and 3 signals are
present only when the 4262A is equipped with
option(s). The INT REQ signal is sent to A23 and
the INT ACK signal actuates the Multiplexer so
that the vector address and keyboard address
signals pass through the Multiplexer toward the
DATA BUS line.
The Annunciator Register stores manifold annun-
ciation data which are serially transferred from the
Nanoprocessor to each register file of IC's U7, U8
and U15 through U21. Specifically, U15 stores test
signal annunciation data and, additionally, origi-
nates the test signal control signals which direct the
Low Level, 120kHz, 1kHz and 10kHz measure-
ment functions. U8 also originates the CMS
(Circuit Mode Selection) signal. When the nano-
Section VIII
Paragraphs 8-31 to 8-33
processor is transferring the annunciation data, the
Data Bus Driver/Receiver is set to receiver mode.
8-32. A22 DISPLAY CONTROL & RAM.
A22 section consists of three major circuits:
Display control, Extender RAM and Clock gen-
erator. The Display control does conversion and
storage of measured data to be displayed on the
seven segment numeric display. When the Nano-
processor begins to transfer measured counts (8 bit
BCD signal), the Data Bus Driver/Receiver (U19 &
U20) is set to receiver mode. L, C or R count data
passes through the Data Bus Driver/Receiver and D
or Q count data follows. These signals are simul-
taneously routed to both the Multiplexer (U10 &
U18) and the BCD to Seven Segment Decoder
(U5). When the measured data is being transferred,
the Multiplexer continues selecting BCD to seven
segment decoder output signals from its two
channel input signals. Other signals, fed directly
from the Data Bus Driver/Receiver, are disregarded,
Thus, the measured data is translated into segment
data which is coded as appropriate for driving the
seven segment numeric displays and, is successively
stored in the Display Register File (U9 & U17) to
accomplish matrix drive of display. The Display
Register File outputs the display segment signals
which alternately illuminate the numeric figure of
each measured count digit of the displays. These
display segment signals are amplified to supply
sufficient current to the LED displays (cathode
driver output signals CAT1 - CAT8). The Scan
Decoder Ul outputs periodic anode scan signals
which activate, in sequence, the display for each
digit. Both the Display Register File and the Scan
Decoder are simultaneously driven by Scan
Counter U2. a
Alphabetic annunciations— PASS, FAIL, O-F and
U-CL— are displayed in the following manner: the
nanoprocessor encodes annunciation contents so
that the annunciation data comprises the display
segment signals appropriate for displaying annun-
ciation figures. The annunciation data passes
through the Data Bus Driver/Receiver and is
inputted to the Multiplexer. In the annunciation
execute phase, the Multiplexer selects the annun-
ciation data and disregards the (unnecessary)
signals from the BCD to Seven Segment Decoder.
The Display Register File stores the annunciation
data which coincides directly with the display
segment signals. The Data Bus Driver/Receiver can
be set to driver mode when the Integrator test
switch is set to TST position or the instrument is
triggered externally. The Extender RAM (U22)
performs supplementary storage of data which is
inputted or outputted to/from the Nanoprocessor.
The Nanoprocessor sends address signals to the
Address Register (U21) before storing data in the
8-11