Digital Control Section; A23 Processor And Rom - HP 4262A Operating And Service Manual

Section VIII
Paragraphs 8-28 to 8-31
8-28. DIGITAL CONTROL SECTION.
8-29. Paragraphs 8-29 discusses how the 4262A
digital section controls the analog section to
measure LCR and D values of unknown device and
how the built-in nanoprocessor creates unique per-
formance in the 4262A. Figure 8-7 is the basic
block diagram of 4262A digital section. All analog
section control signals except for Test Signal and
Circuit Mode Control Signals are sequentially out-
putted from A23 Processor & ROM in accord with
nanoprocessor programming. The A21 Keyboard
Control establishes the measurement function as
selected when the front panel control keys are
appropriately depressed. The A21 section also
stores annunciation data and transfers it to A2 Dis-
play and Keyboard to display the annunciation
information. A22 Display Control and RAM con-
verts measured data transmitted from A23 into
signals appropriate for display on the numeric dis-
plays (A2). The A21, A22,and A23 sections are
connected to the bidirectional DATA BUS LINE
(8 bit).
8-30. A23 PROCESSOR AND ROM.
8-10
Model 4262A
The Nanoprocessor accesses its program data
simultaneously by addressing the ROM while the
ROM outputs the nanoprocessor program codes.
When the ROM outputs an analog section control
signal or while measured data is being transferred
through the Data Bus line, the Nanoprocessor is
not accessing. The Nanoprocessor sequentially
excutes program steps in accord with the program
data given by the ROM. Various timing in the
digital section is controlled by Device Select Code
signals (4 bit). These timing control signals are
decoded to DSR (Device Select: Read) and DSW
(Device Select: Write) signals and manipulate the
individual devices, respectively, of the digital
section as follows:
DSR: Causes Register or Memory to output
data or sets Data Bus Driver/Receiver to
driver mode. Nanoprocessor accesses
(reads) the data sent from Memory or
Data Bus Driver/receiver.
DSW: Enables Register or Memory to store
data or sets Data Bus Driver/Receiver to
receiver mode. Nanoprocessor sends
(writes out) data to Register, Memory or
Data Bus Driver/Receiver.
The Device Select Decoder (U3 and U4) each have
15 DSR and DSW output ports.
When 4262A function is selected or changed, the
INT. REQ (INTerrupt REQuest) control line goes
to high level. This INT. REQ signal requests the
Nanoprocessor to pause before proceeding with the
nanoprocessor program and to manage the
function control prior to program processes. The
INT. REQ control line is always active so as to
allow for servicing of interrupt requests. The INT,
ACK (INTerrupt ACKnowledge) line momentarily
goes high to make the vector address line valid.
The Nanoprocessor accesses the vector address
code (VAQ and VA1) to discriminate which
control (or controller) originated the interrupt
request. When the INT ACK line is at high level,
interrupt control data is inputted to the nano-
processor via A21 Keyboard Control. Successively,
the INT ENA (INTerrupt ENAble) output line is
set to '"disable" status so as not to allow a second
interruption before the present interrupt is pro-
cessed and ends. The INT ENA line is also con-
trolled in the program execute phase (specifically,
this output line performs a '"handshake" function
when the 4262A is used as a component in an
HP-IB system).