Positive Sequence Undervoltage Protection; Positive Sequence Undervoltage Implementation; Positive Sequence Undervoltage Logic; Figure 107: Positive Sequence Undervoltage Logic - GE MiCOM P40 Agile Technical Manual

Chapter 10 - Voltage Protection Functions
7

POSITIVE SEQUENCE UNDERVOLTAGE PROTECTION

7.1

POSITIVE SEQUENCE UNDERVOLTAGE IMPLEMENTATION

Positive Sequence Undervoltage Protection is implemented under the POS SEQ U/V heading in the VOLT
PROTECTION Voltage column of the relevant settings group.
The product provides two stages of Positive Sequence Undervoltage protection with independent time delay
characteristics.
Stage 1 provides a choice of operate characteristics, where you can select between:
● An IDMT characteristic
DT (Definite Time)
●
You set this using the V1<1 Function cell.
The IDMT characteristic is defined by the following formula:
t = K/( M-1)
where:
K = Time multiplier setting
●
t = Operating time in seconds
●
● M = Measured voltage / IED setting voltage
There is no Timer Hold facility for Undervoltage.
Stage 2 can have definite time characteristics only. This is set in the V1<2 status cell.
Two stages are included in order to provide multiple output types, such as alarm and trip stages.
7.2

POSITIVE SEQUENCE UNDERVOLTAGE LOGIC

V1
V1<1 Voltage Set
V1<1 Time Delay
All Poles Dead
V<1 Poledead Inh
Enabled
VTS Block 1
Enabled
VTS Fast Block
V1<1 Timer Block

Figure 107: Positive Sequence Undervoltage logic

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Note : This diagram does not show all stages . Other stages follow similar principles.
VTS Fast Block only applies for directional models .
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P14D
V1<1 Start
V1<1 Trip
V00816
P14D-TM-EN-8