Expansion Interface; Jtag Emulation Port - Analog Devices ADSP-21160 EZ-KIT Lite System Manual

System Architecture

Expansion Interface

The expansion interface consists of three unpopulated connectors.
Table 3-1 shows the interfaces each connector provides. For the exact
pinout of these connectors, refer to
Devices does not populate these connectors or provide any additional sup-
port for this interface. The mechanical dimensions of the connectors can
be found in "Board Current Measurements" on page
Table 3-1. Expansion Interface Connectors
Connector Interfaces
5V, GND, Address[31–0], Data[47–0]
P1
3.3V, GND, FLAG[3–0], SPORT1, ~IRQ[2–0], TIMEXP
P2
GND, Reset, LINKPORT2, memory control signals, D[63-–8]
P3
Limits to the current and to the interface speed must be taken into consid-
eration when using the expansion interface. The maximum current limit is
dependent on the capabilities of the regulator. Additional circuitry can
also add extra loading to signals, decreasing their maximum effective
speed.
Analog Devices does not support and is not responsible for the
effects of additional circuitry.

JTAG Emulation Port

The JTAG emulation port allows an emulator to access the processor's
internal and external memory, as well as the special function registers,
through a 14-pin interface. When an emulator connects to the board at
, the USB debugging interface is disabled.
P8
3-4
Appendix B,
ADSP-21160 EZ-KIT Lite Evaluation System Manual
"Schematics". Analog
3-14.