Table 51. Rain Max For F Adc = 14 Mhz - STMicroelectronics STM32F031F4 Manual

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Electrical characteristics
Symbol Parameter
ADC_DR register write
(2)
W
LATENCY
latency
(2)
t Trigger conversion latency
latr
ADC jitter on trigger
Jitter
ADC
conversion
(2)
Sampling time
t
S
(2)
t Power-up time
STAB
Total conversion time
(2)
t
CONV
(including sampling time)
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I
on I should be taken into account.
DD
2. Guaranteed by design, not tested in production.
Equation 1: R

R
AIN
The formula above
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
T (cycles)
s
1.5
7.5
13.5
28.5
41.5
76/113
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Table 50. ADC characteristics (continued)
ADC clock = HSI14
ADC clock = PCLK/2
ADC clock = PCLK/4
f = f
ADC
f
f = f
ADC
f
f
ADC
f
ADC
f
ADC
max formula
AIN
T
S
------------------------------------------------------------- - R
N +
  
f C ln 2
ADC ADC
(Equation 1) is used to determine the maximum external impedance
Table 51. R
AIN
DocID025743 Rev 3
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Conditions
1.5 ADC
cycles + 2
f
PCLK
/2 = 14 MHz
PCLK
= f /2
ADC PCLK
/4 = 12 MHz
PCLK
= f /4
ADC PCLK
= f = 14 MHz
HSI14
f = f
ADC HSI14
= 14 MHz
-
-
= 14 MHz
14 to 252 (t
-
successive approximation)
–
ADC
2

max for f = 14 MHz
ADC
t (µs)
S
0.11
0.54
0.96
2.04
2.96
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STM32F031x4 STM32F031x6
Min Typ Max
1.5 ADC
cycles + 3
-
f
cycles
PCLK
- 4.5
- 8.5
0.196
5.5
0.219
10.5
0.188 - 0.259
- 1
0.107 - 17.1
1.5 - 239.5
- -
1 -
for sampling +12.5 for
S
R max (k)
AIN
0.4
5.9
11.4
25.2
37.2
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Unit
cycles
f
PCLK
-
cycle
f
PCLK
-
cycle
µs
1/f
PCLK
µs
1/f
PCLK
µs
- 1/f
HSI14
µs
1/f
ADC
Conver
1 sion
cycle
18 µs
1/f
ADC
and 60 µA
DDA
(1)
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