8.1
Programming reference
Control interface: 2 channels, 24 output bytes (Q addresses)
CPU input address
Channel 0
Channel 1
DWord 0
DWord 12
DWord 4
DWord 16
Byte 8: Bits 0
Byte 20: Bits 0 to 3
to 3
Byte 8: Bit 4
Byte 20: Bit 4
Technology module TM Pulse 2x24V (6ES7138‑6DB00‑0BB1)
Manual, 09/2015, A5E35061186-AA
Description
1
Depending on the mode:
Pulse output mode: Pulse duration in μs
•
PWM mode: Duty cycle On-ratio (Number range set by Output format configuration)
•
–
"Per 100": 0 to 100
–
"Per 1000": 0 to 1,000
–
"Per 10000": 0 to 10,000
–
"S7 analog output": 0 to 27,648
PWM mode with current control: Target current is assigned as a ratio of target cur-
•
rent/reference current
Pulse train mode: Number of pulses to output as a DWord number value between 1 to
•
4,294,967,295 (2
On/Off-delay mode: Off-delay in μs
•
Frequency output mode: Output frequency in Hz
•
SLOT value: Behavior depends on operating mode, MODE_SLOT(1 bit), and LD_SLOT (four
bits).
LD_SLOT value controls interpretation of SLOT value.
0 = No action / idle state
•
1 = Period duration μs (PWM, Pulse train, and DC motor)
•
2 = On-delay μs (Pulse output, PWM, Pulse train, Frequency output, and DC motor)
•
3 = Off-delay μs (On/Off-delay)
•
4 = Duty cycle On-ratio (Pulse train)
•
5 = Dither ramp-up time and ramp-down time (PWM)
•
6 = Dither amplitude (PWM)
•
7 = Dither period (PWM)
•
MODE_SLOT value controls the SLOT update process.
0 = single update (SLOT changed sometimes, prior to output sequence)
•
1= permanent update (SLOT controlled continuously)
•
-1)
32
Technical specifications
8.1 Programming reference
131