Pci Express Gen2 Root Port; Low Pin Count (Lpc) Interface; Serial Peripheral Interface (Spi); Uart Interface - Advantech sky-8100 User Manual

1u carrier grade server based on processor intel xeon-d series
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2.3.10 PCI Express Gen2 Root Port

- Supporting the PCI Express Base Specification, Revision 2.0.
- One PCIe Gen2 x4 to Intel I350 LAN Controller
- Two PCIe Gen2 x1 to Intel I210 LAN Controller
- One PCIe Gen1 x1 to LOM Connector (BMC Module)
Broadwell-DE

Figure 2-15: Broadwell-DE PCIe Express Gen2 Block Diagram for SKY-8100MB

2.3.11 Low Pin Count (LPC) Interface

- Supporting the LPC 1.1 Specification.
- Connect to TPM and LOM Connectors.
Broadwell-DE

Figure 2-16: Broadwell-DE LPC Block Diagram for NAMB-3260MB

2.3.12 Serial Peripheral Interface (SPI)

- SPI Interface as an Alternative Interface for the BIOS Flash Device.
- Support Redundant BIOS.

2.3.13 UART Interface

- Two UART Ports Only Provide Transmit (TXD) and Receiver (RXD) Signals.
- Default Baud Rate is 115200 and Be Set in BIOS.
SKY-8100 Manual V05 20161229
PCIe 2.0 x4
PCIe 2.0 x2
PCIe 2.0 x1
LPC
Copyright 2016 Advantech Co. Ltd. All rights reserved.
LAN Controller
I350
LAN Controller
I210
LOM
Connector
TPM
Connector
LOM
Connector
x2
Page 47

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