Eaton EDR 3000 Installation, Operation And Maintenance Manual page 744

Name
Logic.LE29.Timer Out
Logic.LE29.Out
Logic.LE29.Out inverted
Logic.LE29.Gate In1-I
Logic.LE29.Gate In2-I
Logic.LE29.Gate In3-I
Logic.LE29.Gate In4-I
Logic.LE29.Reset Latch-I
Logic.LE30.Gate Out
Logic.LE30.Timer Out
Logic.LE30.Out
Logic.LE30.Out inverted
Logic.LE30.Gate In1-I
Logic.LE30.Gate In2-I
Logic.LE30.Gate In3-I
Logic.LE30.Gate In4-I
Logic.LE30.Reset Latch-I
Logic.LE31.Gate Out
Logic.LE31.Timer Out
Logic.LE31.Out
Logic.LE31.Out inverted
Logic.LE31.Gate In1-I
Logic.LE31.Gate In2-I
Logic.LE31.Gate In3-I
Logic.LE31.Gate In4-I
Logic.LE31.Reset Latch-I
Logic.LE32.Gate Out
Logic.LE32.Timer Out
Logic.LE32.Out
Logic.LE32.Out inverted
Logic.LE32.Gate In1-I
Logic.LE32.Gate In2-I
Logic.LE32.Gate In3-I
Logic.LE32.Gate In4-I
Logic.LE32.Reset Latch-I
Logic.LE33.Gate Out
Logic.LE33.Timer Out
Description
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
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EDR-3000 IM02602003E
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