Clock Synchronization; Frequency Tracking And Phase Locking - GE L90 Instruction Manual

8.1 OVERVIEW
2
( ) (
I I
=
REST_A LOC_PHASOR_RESTRAINT_A
The fault severity for each phase is determined by following equation:
where P is the pickup setting.
This equation is based on the adaptive strategy and yields an elliptical restraint characteristic. The elliptical area is the
restraint region. When the adaptive portion of the restraint current is small, the restraint region shrinks. When the adaptive
portion of the restraint current increases, the restraint region grows to reflect the uncertainty of the measurement. The com-
puted severity increases with the probability that the sum of the measured currents indicates a fault. With the exception of
"Restraint", all quantities are defined in previous sections. "Adaptive Restraint" is a restraint multiplier, analogous to the
slope setting of traditional differential approaches, for adjusting the sensitivity of the relay.
Raising the restraint multiplier corresponds to demanding a greater confidence interval, and has the effect of decreasing
sensitivity while lowering it is equivalent to relaxing the confidence interval and increases sensitivity. Thus, the restraint
multiplier is an application adjustment that is used to achieve the desired balance between sensitivity and security. The
computed severity is zero when the operate phasor is on the elliptical boundary, is negative inside the boundary, and posi-
tive outside the boundary. Outside of the restraint boundary, the computed severity grows as the square of the fault current.
The restraint area grows as the square of the error in the measurements.
Synchronization of data sampling clocks is needed in a digital differential protection scheme, because measurements must
be made at the same time. Synchronization errors show up as phase angle and transient errors in phasor measurements at
the terminals. By phase angle errors, we mean that identical currents produce phasors with different phase angles. By tran-
sient errors, we mean that when currents change at the same time, the effect is seen at different times at different measure-
ment points. For best results, samples should be taken simultaneously at all terminals.
In the case of peer to peer architecture, synchronization is accomplished by synchronizing the clocks to each other rather
than to a master clock. Each relay compares the phase of its clock to the phase of the other clocks and compares the fre-
quency of its clock to the power system frequency and makes appropriate adjustments. The frequency and phase tracking
algorithm keeps the measurements at all relays within a plus or minus 25 microsecond error during normal conditions for a
2 or 3 terminal system. For 4 or more terminals the error may be somewhat higher, depending on the quality of the commu-
nications channels. The algorithm is unconditionally stable. In the case of 2 and 3 terminal systems, asymmetric communi-
cations channel delay is automatically compensated for. In all cases, an estimate of phase error is computed and used to
automatically adapt the restraint region to compensate. Frequency tracking is provided that will accommodate any fre-
quency shift normally encountered in power systems.
Each relay has a digital clock that determines when to take data samples and which is phase synchronized to all other
clocks in the system and frequency synchronized to the power system frequency. Phase synchronization drives the relative
timing error between clocks to zero, and is needed to control the uncertainty in the phase angle of phasor measurements,
8
which will be held to under 26 microseconds (0.6 degrees). Frequency synchronization to the power system eliminates a
source of error in phasor measurements that arises when data samples do not exactly span one cycle.
The block diagram for clock control for a two terminal system is shown in Figure 8–4. Each relay makes a local estimate of
the difference between the power system frequency and the clock frequency based on the rotation of phasors. Each relay
also makes a local estimate of the time difference between its clock and the other clocks either by exchanging timing infor-
mation over communications channels or from information that is in the current phasors, depending on whichever one is
more accurate at any given time. A loop filter then uses the frequency and phase angle deviation information to make fine
adjustments to the clock frequency. Frequency tracking starts if the current at one or more terminals is above 0.125 pu of
nominal; otherwise, the nominal frequency is used.
8-4
2
) (
I
+
REM1_PHASOR_RESTRAINT_A
2 2
( ) ( (
S I 2P I
= – +
A DIFF_A REST_A

8.1.8 FREQUENCY TRACKING AND PHASE LOCKING

L90 Line Differential Relay
8 THEORY OF OPERATION
2
) (
I
+
REM2_PHASOR_RESTRAINT_A
2
) )

8.1.7 CLOCK SYNCHRONIZATION

2
)
(EQ 8.10)
(EQ 8.11)
GE Multilin