Hardware Architecture; Memory And Real Time Clock; Figure 3: Hardware Design Overview - GE P24DM Technical Manual

Chapter 3 - Hardware Design
2

HARDWARE ARCHITECTURE

The main components comprising devices based on the P40Agile platform are as follows:
The housing, consisting of a front panel and connections at the rear
●
The Main processor module consisting of the main CPU (Central Processing Unit), memory and an interface
●
to the front panel HMI (Human Machine Interface)
An I/O board consisting of output relay contacts and digital opto-inputs
●
● Communication modules
Power supply
●
All modules are connected by a parallel data and address bus, which allows the processor module to send and
receive information to and from the other modules as required. There is also a separate serial data bus for
conveying sampled data from the input module to the CPU. These parallel and serial databuses are shown as a
single interconnection module in the following figure, which shows typical modules and the flow of data between
them.
Keypad
LCD
LEDs
Front port
Super capacitor-backed
Watchdog
contacts Watchdog module
+ LED
Auxiliary
Supply
* No VTs on current - only models. No CTs on voltage-only models
V00200

Figure 3: Hardware design overview

2.1

MEMORY AND REAL TIME CLOCK

The IED contains flash memory for storing the following operational information:
Fault, Maintenance and Disturbance Records
●
Events
●
Alarms
●
Measurement values
●
● Latched trips
Latched contacts
●
30
Memory
Flash memory for all
settings and records
DRAM
for real-time clock
PSU module
Output relay module
Opto-input module
I/O
CTs
VTs
Analogue Inputs
RS485 module
IRIG-B module
Ethernet module
Communications
P24xM
Output relay contacts
Digital inputs
Power system currents *
Power system voltages *
RS485 communication
Time synchronisation
(Optional)
Ethernet communication
(Optional)
P24xM-TM-EN-2.1