Pci Express® Differential Clock Ac Specifications; Timing Requirements For Refclk_P Used As Oscin (14.3181818Mhz); Side-Port Memory Timing For Ddr2 Mode; Read Cycle Dq/Dqs Delay - AMD 780E Technical Reference Manual

4.3 PCI Express ® Differential Clock AC Specifications

Table 4-2 PCI-E Differential Clock (GFX_REFCLK, GPPSB_REFCLK, 100MHz) AC Characteristics

Symbol
Rising Edge Rate
Falling Edge Rate
T
PERIOD AVG
T
PERIOD ABS
T
CCJITTER
Duty Cycle
Rise-Fall Matching
4.4

Timing Requirements for REFCLK_P Used as OSCIN (14.3181818MHz)

Table 4-3 Timing Requirements for REF_CLKP Used as OSCIN (14.3181818MHz)

Symbol
TIP REFCLK Period
TIH REFCLK High Time
TIL REFCLK Low Time
TIR REFCLK Rise Time
TIF REFCLK Fall Time
TIRR REFCLK Rising Edge Rate
TIFR REFCLK Falling Edge Rate
TIDC Duty Cycle
TIJCC REFCLK Cycle-to-Cycle Jitter Requirement
TIJPP REFCLK Peak-to-Peak Jitter Requirement
REFCLK Long Term Jitter Requirement (1s after
TIJLT
scope trigger)
Notes:
1. Measured from -150mV to + 150mV from VREF, which is 0.55V.
2. Measured at VREF, which is 0.55V.
3. Measured with spread spectrum disabled.
4.5

Side-port Memory Timing for DDR2 Mode

The RS780E's side-port memory DDR2 interface complies with all the timing requirements given in the JESD79-2B
specification. Please refer to the JEDEC standard for any timing details.
4.5.1

Read Cycle DQ/DQS Delay

During a memory read cycle, there is a DLL inside the RS780E that can delay each DQS signal with respect to its byte of
the DQ valid window. This delay ensures adequate setup and hold time to capture the memory data. This DLL delay is
programmable through the following registers:
MCA_DLL_SLAVE_RD_0. MCA_DLL_ADJ_DQSR_0 <NBMCIND : 0xE0[7:0]>
MCA_DLL_SLAVE_RD_1. MCA_DLL_ADJ_DQSR_1 <NBMCIND : 0xE1[7:0]>
The fraction of strobe delay, in terms of a memory clock period is (24+MCA_DLL_ADJ_DQSR) / 240. For example: if
MCA_DLL_ADJ_DQSR_1 = 36, then DQS1 is delayed by 0.25 x memory_clock_period. So, if the memory clock period
is 5ns, then DQS1 is delayed internally by 1.25ns with respect to DQ[15:8].
45732 AMD 780E Databook 3.10
4-2
Description
Rising Edge Rate
Falling Edge Rate
Average Clock Period Aquaria
Absolute Period (including jitter and spread spectrum
modulation)
Cycle to Cycle Jitter
Duty Cycle
Rising edge rate (REFCLK+) to falling edge rate
(REFCLK-) matching
Parameter
PCI Express® Differential Clock AC Specifications
Minimum
0.6
0.6
-300
9.847
-
40
-
Min Max Unit
69.82033 69.86224
2.0 –
2.0 –
– 1.5 ns
– 1.5 ns
0.09 4.0 V/ns
0.09 4.0 V/ns
45 55
– 300
– 200
– 500
© 2009 Advanced Micro Devices, Inc.
Maximum Unit
4.0 V/ns
4.0 V/ns
+2800 ppm
10.203 ns
150 Ps
60 %
20 %
Note
ns
ns
ns
1
1
% 2
ps 3
ps 2, 3
ps
Proprietary