Pmc - Power Management Capabilities (Offset = 2); Table 6-10 Power Management Capabilities - Pmc - AMD 780E Technical Reference Manual

6.2.7

PMC - Power Management Capabilities (Offset = 2)

The Power Management Capabilities register is a 16-bit Read Only register that provides information on the capabilities
of the function related to power management. The information in this register is generally static and is known at design
time.
Table 6-10 Power Management Capabilities – PMC
Bits Default Value
15:11 00111b
10 001b
09 001b
08:06 000b
05 1b
04 0b
03 0b
02:00 001b
45732 AMD 780E Databook 3.10
6-6
Read/
Write
Read Only This 5-bit field indicates the power states in which the function may assert PME#. A value of
0b for any bit indicates that the function is not capable of asserting the PME# signal while in
that power state.
bit(11) XXXX1b - PME# can be asserted from D0.
bit(12) XXX1Xb - PME# can be asserted from D1.
bit(13) XX1XXb - PME# can be asserted from D2.
bit(14) X0XXXb - PME# cannot be asserted from D3hot.
bit(15) 0XXXXb - PME# cannot be asserted from D3cold.
Read Only RS780E supports D2.
Read Only RS780E supports D1.
Read Only Reserved
Read Only The Device Specific Initialization bit indicates whether special initialization of this function is
required (beyond the standard PCI configuration header) before the generic class device
driver is able to use it. The RS780E requires device specific initialization after Reset; this field
must therefore return a value 1 to the system.
Read Only Reserved
Read Only Reserved
Read Only A value of 001b indicates that this function complies with Revision 1.0 of the PCI Power
Management Interface Specification.
Power Management for the Graphics Controller
Description
© 2009 Advanced Micro Devices, Inc.
Proprietary