AMD Athlon™ XP Processor Model 6 Data Sheet
7.10
SYSCLK and SYSCLK# AC and DC Characteristics
Table 9.
SYSCLK and SYSCLK# DC Characteristics
Symbol
V
Crossing before transition is detected (DC)
Threshold-DC
V
Crossing before transition is detected (AC)
Threshold-AC
I
Leakage current through P-channel pullup to VCC_CORE
LEAK_P
I
Leakage current through N-channel pulldown to VSS (Ground)
LEAK_N
V
Differential signal crossover
CROSS
C
Capacitance *
PIN
Note:
* The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.
32
Preliminary Information
Table 9 shows the DC characteristics of the SYSCLK and
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together.
Description
Figure 9 shows the DC characteristics of the SYSCLK and
SYSCLK# signals.
V
CROSS
Figure 9. SYSCLK and SYSCLK# Differential Clock Signals
Electrical Data
Min
400
450
–250
VCC_CORE/2
4
V
= 400mV
V
Threshold-DC
24309E—March 2002
Max
Units
mV
mV
µA
250
µA
mV
±100
12
pF
= 450mV
Threshold-AC
Chapter 7
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