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26237C—May 2003
8.9
SYSCLK and SYSCLK# DC Characteristics
Table 15. SYSCLK and SYSCLK# DC Characteristics
Symbol
Crossing before transition is detected (DC)
V
Threshold-DC
Crossing before transition is detected (AC)
V
Threshold-AC
Leakage current through P-channel pullup to V
I
LEAK_P
Leakage current through N-channel pulldown to VSS (Ground)
I
LEAK_N
Differential signal crossover
V
CROSS
C
Capacitance *
PIN
Note:
* The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.
Chapter 8
Preliminary Information
Table 15 shows the DC characteristics of the SYSCLK and
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together. For more
information about SYSCLK and SYSCLK#, see "SYSCLK and
S Y S C L K # " o n p a g e 7 7 a n d Ta b l e 2 3 , " P i n N a m e
Abbreviations," on page 56.
Description
Figure 11 shows the DC characteristics of the SYSCLK and
SYSCLK# signals.
V
CROSS
Figure 11. SYSCLK and SYSCLK# Differential Clock Signals
Electrical Data
AMD Athlon™ XP Processor Model 10 Data Sheet
Min
400
450
–1
CC_CORE
4
V
= 400mV
Threshold-DC
Max
Units
mV
mV
mA
1
mA
V
/ 2±100
mV
CC_CORE
25 *
pF
V
= 450mV
Threshold-AC
35
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