Lvds; 2.4.1 Lvds Data Mapping; Figure 2-6 Single/Dual Channel 18-Bit Lvds Data Transmission Ordering - AMD 780E Technical Reference Manual

LVDS

2.4 LVDS
The RS780E's LVTM interface can operate as a dual-channel 18-/24-bit LVDS interface. Notice that for designs
implementing only a single LVDS channel, the LOWER channel of the interface should be used.

2.4.1 LVDS Data Mapping

Figure 2-6 shows the transmission ordering of the LVDS signals for 18-bit transmission on the lower and the upper data
channels. The signal mappings for single and dual channel transmission are shown in
respectively.
Figure 2-7 shows the transmission ordering of the LVDS signals for 24-bit transmission on the lower and the upper data
channels. The signal mappings for single and dual channel transmission are shown in
respectively.
TXCLK_L-/+
TXOUT_L0-/+
TXOUT_L1-/+
TXOUT_L2-/+
TXCLK_U-/+
TXOUT_U0-/+
TXOUT_U1-/+
TXOUT_U2-/+

Figure 2-6 Single/Dual Channel 18-bit LVDS Data Transmission Ordering

© 2009 Advanced Micro Devices, Inc.
Proprietary
T Cycle
LP1C7 LP1C6 LP1C5 LP1C4
LP2C7 LP2C6 LP2C5 LP2C4
LP3C7 LP3C6 LP3C5 LP3C4
T Cycle
UP1C7 UP1C6 UP1C5 UP1C4
UP2C7 UP2C6 UP2C5 UP2C4
UP3C7 UP3C6 UP3C5 UP3C4
Table 2-5
Table 2-9
LP1C3 LP1C2 LP1C1
LP2C3 LP2C2 LP2C1
LP3C3 LP3C2 LP3C1
UP1C3 UP1C2 UP1C1
UP2C3 UP2C2 UP2C1
UP3C3 UP3C2 UP3C1
45732 AMD 780E Databook 3.10
and Table 2-6
and Table 2-10
2-7