Pixel Format Image; Pin Description - Advantech IDK-121R-42XGA1 User Manual

3.1

Pixel Format Image

The following figure shows the relationship between the input signal and the
LCD pixel format.
3.1.1

Pin Description

Table 3.1: Pin Description
Pin No. Symbol
1 VDD
2 VDD
3 GND
4 SEL68
5 RIN0-
6 RIN0+
7 GND
8 RIN1-
9 RIN1+
10 GND
11 RIN2-
12 RIN2+
13 GND
14 RCLKIN-
15 RCLKIN+
16 GND
17 RIN3-
18 RIN3+
19 RSV
20 NC/GND
IDK-1112R User Manual
Description
Power supply,3.3V (typical)
Power supply,3.3V (typical)
Ground
6 / 8-bits LVDS data input selection [H: 8bits L/NC: 6bit] *Note 4
LVDS differential signal channel 0
LVDS differential data input (R0, R1, R2, R3, R4, R5, G0)
Ground
LVDS differential signal channel 1
LVDS differential data input (G1, G2, G3, G4, G5, B0, B1)
Ground
LVDS differential signal channel 2
LVDS differential data input (B2, B3, B4, B5, HS, VS, DE)
Ground
LVDS receiver signal clock
Ground
LVDS receiver signal channel 3, NC for 6 bit LVDS Input *Note 5
LVDS differential data input (R6, R7, G6, G7, B6, B7, RSV)
Reverse scan function [H: Enable; L/NC: Disable]
Reserved for AUO internal test. Please treat it as NC.
12