Pixel Format Image; Pin Description - Advantech IDK-1121WR-30FHA1E User Manual

3.1

Pixel Format Image

Following figure shows the relationship between input signal and LCD pixel
format.
3.2

Pin Description

The module using a pair of LVDS receiver SN75LVDS82 (Texas Instruments) or
compatible. LVDS is a differential signal technology for LCD interface and high speed
data transfer device. Transmitter shall be SN75LVDS83 (negative edge sampling) or
compatible. The first LVDS port (RxOxxx) transmits odd pixels while the second
LVDS port (RxExxx) transmits even pixels.
Table 3.1: Pin Description
Pin No. Symbol
1 RxO0-
2 RxO0+
3 RxO1-
4 RxO1+
5 RxO2-
6 RxO2+
7 VSS
8 RxOC-
9 RxOC+
10 RxO3-
11 RxO3+
12 RxE0-
13 RxE0+
14 VSS
IDK-1121W User Manual
Description
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Odd data, H-Sync,V-
Sync,DSPTMG)
Positive LVDS differential data input (Odd data, H-Sync,V-
Sync,DSPTMG)
Power Ground
Negative LVDS differential clock input (Odd clock)
Positive LVDS differential clock input (Odd clock)
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Power Ground
14