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Errata
13.
Processor May Hang Due to Speculative Page Walks to Non-Existent
System Memory
Problem:
A load operation that misses the Data Translation Lookaside Buffer (DTLB) will result
in a page-walk. If the page-walk loads the Page Directory Entry (PDE) from cacheable
memory and that PDE load returns data that points to a valid Page Table Entry (PTE)
in uncacheable memory the processor will access the address referenced by the PTE.
If the address referenced does not exist the processor will hang with no response
from system memory.
Implication: Processor may hang due to speculative page walks to non-existent system memory.
Workaround:
Page directories and page tables in UC memory space which are marked valid
must point to physical addresses that will return a data response to the processor.
Status:
For the steppings affected, see the Summary Tables of Changes.
14.
Load Operations May Get Stale Data in the Presence of Memory
Address Aliasing
Problem:
Aliasing refers to multiple logical addresses referencing the same physical address in
memory. When multiple stores to the same physical memory location are pending in
the processor, the processor must ensure that a subsequent instruction, which loads
data from that same physical memory location, receives the data from the most
recent store. When there are two pending stores in the processor to the same
physical memory address, and the more recent store uses a different logical address
to reference the same physical address, it is possible that a subsequent load from the
same physical address may incorrectly receive the data based on the older store,
rather than the most recently executed store.
Implication: When this erratum occurs, stale data will be loaded.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
15.
Writing a Performance Counter May Result in Incorrect Value
Problem:
When a performance counter is written and the event counter for the event being
monitored is non-zero, the performance counter will be incremented by the value on
that event counter. Because the upper eight bits of the performance counter are not
written at the same time as the lower 32 bits, the increment due to the non-zero
event counter may cause a carry to the upper bits such that the performance counter
contains a value about four billion (2
Implication: When this erratum occurs, the performance counter will contain a different value
from that which was written.
Workaround:
If the performance counter is set to select a null event and the counter
configuration and control register (CCCR) for that counter has its compare bit set to
zero, before the performance counter is written, this erratum will not occur. Since the
lower 32 bits will always be correct, event counting which does not exceed 2
will not be affected.
Specification Update
32
) higher than what was written.
32
events
35
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