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Workaround:
Remove the software's dependency on #AC having precedence over #PF.
Alternately, correct the page fault in the page fault handler and then restart the
faulting instruction.
Status:
For the steppings affected, see the Summary Tables of Changes.
10.
IERR# May Not go Active When an Internal Error Occurs
Problem:
If the processor hangs because a store to the system bus does not complete, the
processor may not assert the IERR# signal.
Implication: When this erratum occurs, IERR# is not signaled.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
11.
All L2 Cache Uncorrectable Errors Are Logged As Data Writes
Problem:
When a Data Read operation which hits the L2 cache gets an uncorrectable error, the
processor should log this error in the IA32_MC1_STATUS register as a Data Read by
setting bits 7-4 to 0011b. The processor incorrectly logs Data Read operations, which
hit the L2 cache and receive an uncorrectable error, with the bit pattern 0100b,
indicating a Data Write Operation.
Implication: Data Read operations, which cause an uncorrectable error, are logged as Data Write
operations.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
12.
When in No-Fill Mode the Memory Type of Large Pages Are
Incorrectly Forced to Uncacheable
Problem:
When the processor is operating in No-Fill Mode (CR0.CD=1), the paging hardware
incorrectly forces the memory type of large (PSE-4M and PAE-2M) pages to
uncacheable (UC) memory type regardless of the MTRR settings. By forcing the
memory type of these pages to UC, load operations, which should hit valid data in
the L1 cache, are forced to load the data from system memory. Some applications
will lose the performance advantage associated with the caching permitted by other
memory types.
Implication: This erratum may result in some performance degradation when using no-fill mode
with large pages.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
34
Errata
Specification Update
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