Table of Contents
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Summary Tables of Changes
No.
B2
C1
D0
N56
X
X
X
N57
X
X
X
N58
X
X
X
N59
N60
N61
X
X
X
N62
X
X
X
N63
X
X
X
N64
N65
X
X
X
N66
X
X
X
N67
X
X
X
N68
X
X
X
N69
N70
N71
Specification Update
E0
B0
C1
D1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
M0
Plan
Associated counting logic must be
Fixed
configured when using Event Selection
Control (ESCR) MSR
IA32_MC0_ADDR and IA32_MC0_MISC
registers will contain invalid or stale
X
No Fix
data following a Data, Address, or
Response Parity Error
CR2 may be incorrect or an incorrect
page fault error code may be pushed
Fixed
onto stack after execution of an LSS
instruction
BPM[5:3]# V
Fixed
specification
Processor may hang under certain
X
No Fix
frequencies and 12.5% STPCLK# duty
cycle
System may hang if a fatal cache error
causes Bus Write Line (BWL)
transaction to occur to the same cache
X
No Fix
line address as an outstanding Bus
Read Line (BRL) or Bus Read-Invalidate
Line (BRIL)
L2 cache may contain stale data in the
Fixed
Exclusive state
Re-mapping the APIC base address to
a value less than or equal to
Fixed
0xDC001000 may cause IO and Special
Cycle failure
Erroneous BIST result found in EAX
Fixed
register after reset
Processor does not flag #GP on non-
Fixed
zero write to certain MSRs
Simultaneous assertion of A20M# and
X
No Fix
INIT# may result in incorrect data
fetch
CPUID instruction returns incorrect
Fixed
number of ITLB entries
A Write to an APIC Register Sometimes May
X
No Fix
Appear to Have Not Occurred
STPCLK# Signal Assertion under
Plan
X
Certain Conditions May Cause a
Fix
System Hang
Store to Load Data Forwarding may
Fixed
Result in Switched Data Bytes
Parity Error in the L1 Cache may Cause
X
No Fix
the Processor to Hang
ERRATA
does not meet
IL
17
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