Specification Clarifications - Intel BX80623I52500K Specification

Specification Clarifications

The Specification Clarifications listed in this section apply to the following documents:
• Intel
in the 478-pin Package Datasheet
• Intel
• Intel
Intel
Technology Datasheet
• Intel
Land Package Electrical Mechanical and Thermal Specifications (EMTS)
• Intel
2A, 2B, 3A, and 3B: System Programming Guide
All Specification Clarifications will be incorporated into a future version of the
appropriate Pentium 4 processor documentation.
1. SPECIFICATION CLARIFICATION WITH RESPECT TO TIME STAMP
COUNTER
In the "Debugging and Performance Monitoring" chapter (Sections 15.8, 15.10.9 and
15.10.9.3) of the IA-32 Intel
System Programming Guide, the Time Stamp Counter definition has been updated to
include support for the future processors. This change will be incorporated in the next
revision of the IA-32 Intel
15.8 TIME-STAMP COUNTER
The IA-32 architecture (beginning with the Pentium processor) defines a time-stamp
counter mechanism that can be used to monitor and identify the relative time
occurrence of processor events. The counter's architecture includes the following
components:
• TSC flag — A feature bit that indicates the availability of the time-stamp counter.
The counter is available in an IA-32 processor implementation if the function
CPUID.1:EDX.TSC[bit 4] = 1.
• IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family and Pentium
processors) — The MSR used as the counter
• RDTSC instruction — An instruction used to read the time-stamp counter
• TSD flag — A control register flag is used to enable or disable the time-stamp
counter (enabled if CR4.TSD[bit 2] = 1).
The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,
Pentium 4, and Intel Xeon processors) is a 64-bit counter that is set to 0 following a
RESET of the processor. Following a RESET, the counter will increment even when the
70
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Pentium 4 Processor in the 423-pin Package, Intel
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Pentium 4 Processor in the 478-pin Package Datasheet
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Pentium 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and
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Pentium 4 Processor Extreme Edition Supporting Hyper-Threading
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Pentium 4 Processor Extreme Edition on 0.13 Micron Process in the 775-
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64 and IA-32 Intel
®
®
Architecture Software Developer's Manual.
Architectures Software Developer's Manual Volume 1,
Architecture Software Developer's Manual Volume 3:
Specification Clarifications
® ®
Pentium 4 Processor
Specification Update