Intel BX80623I52500K Specification page 20

No. B2 C1 D0
N102 X X X
N103 X X X
N104 X X X
NOTE:
1.
No. B2 C1 D0
No. B2 C1 D0
N1 X X X
No. B2 C1 D0
20
E0 B0 C1 D1
X X X
X X X
X X X
For these steppings, this erratum may be worked around in BIOS.
E0 B0 C1 D1
E0 B0 C1 D1
X X X
E0 B0 C1 D1
M0 Plan
when an Interrupt is Pending May Cause an
Unexpected Interrupt
Using 2M/4M Pages When A20M# Is
X X No Fix Asserted May Result in Incorrect
Address Translations
Writing Shared Unaligned Data that
Crosses a Cache Line without Proper
X X No Fix
Semaphores or Barriers May Expose a
Memory Ordering Issue
Debug Status Register (DR6)
X X No Fix Breakpoint Condition Detected Flags
May be set Incorrectly
M0 Plans
There are no specification changes in
this Specification Update revision.
M0 Plans SPECIFICATION CLARIFICATIONS
Specification clarification with respect
X X Doc
to time stamp counter
M0 Plans
There are no Documentation Changes
in this Specification Update revision.
§
Summary Tables of Changes
ERRATA
SPECIFICATION CHANGES
DOCUMENTATION CHANGES
Specification Update