Intel BX80623I52500K Specification page 15

Summary Tables of Changes
No. B2 C1 D0
N21 X
N22 X X X
N23 X
N24 X
N25 X
N26 X
N27 X
N28 X
N29 X X
N30 X
N31 X
N32 X
N33 X
N34 X
N35 X
N36 X X
N37 X X X
N38 X X X
Specification Update
E0 B0 C1 D1
X X X X
X X X X
X X X X
M0 Plan
register
Processor may hang on a correctable
Fixed
error and snoop combination
The IA32_MC1_STATUS register may
X No Fix contain incorrect information for
correctable errors
MCA error incorrectly logged as
Fixed
prefetches
Speculative loads which hit the L2
Fixed cache and get an uncorrectable error
will log erroneous information
Processor may fetch reset vector from
Fixed
cache if A20M# is asserted during init
A correctable error on an L2 cache
Fixed shared state line hit with go to invalid
snoop hangs processor
System hang due to uncorrectable
Fixed
error and bus lock combination
Incorrect address for an L1 tag parity
Fixed error is logged in IA32_MC1_ADDR
register
REP MOV instruction with overlapping
Fixed source and destination may result in
data corruption
Stale data in processor translation
Fixed
cache may result in hang
I/O buffers for FERR#, PROCHOT# and
Fixed
THERMTRIP# are not AGTL+
RFO and correctable error combination
Fixed
may cause lost store or hang
RFO and correctable error may
Fixed incorrectly signal the machine check
handler
Processor may report invalid TSS fault
Fixed instead of double fault during mode C
paging
IA32_MC0_STATUS incorrect after
Fixed
illegal APIC request
Thermal status log bit may not be set
Fixed when the thermal control circuit is
active
Debug mechanisms may not function
X No Fix
as expected
Machine check architecture error
X No Fix
reporting and recovery may not work
ERRATA
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