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Errata
Implication: Processor may fetch incorrect data, resulting in BIOS failure.
Workaround:
De-asserting and re-asserting A20M# prior to the data access will workaround
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
67.
CPUID Instruction Returns Incorrect Number of ITLB Entries
Problem:
When CPUID instruction is executed with EAX = 2 on a processor without Hyper-
Threading Technology or with Hyper-Threading Technology disabled via power on
configuration, it should return a value of 51h in EAX[15:8] to indicate that the
Instruction Translation Lookaside Buffer (ITLB) has 128 entries. On a processor with
Hyper-Threading Technology enabled, the processor should return 50h (64 entries).
Due to this erratum, the CPUID instruction always returns 50h (64 entries).
Implication: Software may incorrectly report the number of ITLB entries. Operation of the
processor is not affected.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
68.
A Write to APIC Registers Sometimes May Appear to Have Not
Occurred
Problem:
With respect to the retirement of instructions, stores to the uncacheable memory-
based APIC register space are handled in a non-synchronized way. For example, if an
instruction that masks the interrupt flag, e.g. CLI, is executed soon after an
uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority,
the interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but
higher than the final TPR, to not be serviced until the interrupt enabled flag is finally
set, i.e. by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay
their service.
Workaround:
This non-synchronization can be avoided by issuing an APIC register read after
the APIC register write. This will force the store to the APIC register before any
subsequent instructions are executed. No commercial operating system is known to
be impacted by this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
69.
STPCLK# Signal Assertion under Certain Conditions May Cause a
System Hang
Problem:
The assertion of STPCLK# signal before a logical processor awakens from the "Wait-
for-SIPI" state for the first time, may cause a system hang. A processor supporting
Hyper-Threading Technology may fail to initialize appropriately, and may not issue a
Stop Grant Acknowledge special bus cycle in response to the second STPCLK#
assertion.
Specification Update
55
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