Intel BX80605X3430 - Xeon 2.4 GHz Processor Datasheet
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Intel BX80605X3430 - Xeon 2.4 GHz Processor Datasheet

Intel BX80605X3430 - Xeon 2.4 GHz Processor Datasheet

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Intel
Xeon
Processor 3400 Series
Datasheet – Volume 1
June 2010
Document Number: 322371-003

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Summary of Contents for Intel BX80605X3430 - Xeon 2.4 GHz Processor

  • Page 1 ® ® Intel Xeon Processor 3400 Series Datasheet – Volume 1 June 2010 Document Number: 322371-003...
  • Page 2 Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses.

  • Page 3: Table Of Contents

    Dual-Channel Mode—Intel Flex Memory Technology Mode .... 22 2.1.4 Rules for Populating Memory Slots ............23 ® ® 2.1.5 Technology Enhancements of Intel Fast Memory Access (Intel FMA)..24 2.1.5.1 Just-in-Time Command Scheduling..........24 2.1.5.2 Command Overlap ..............24 2.1.5.3 Out-of-Order Scheduling ............
  • Page 4 3.1.4 Intel VT-d Features ................32 ® 3.1.5 Intel VT-d Features Not Supported............33 ® ® Intel Trusted Execution Technology (Intel TXT) ..........33 ® Intel Hyper-Threading Technology ..............34 ® Intel Turbo Boost Technology ................34 Power Management ....................35 ACPI States Supported ..................35 4.1.1 System States..................35...
  • Page 5 7.10.2 Input Device Hysteresis ................78 Processor Land and Signal Information ..............79 Processor Land Assignments ................79 Figures ® ® 1-1 Intel Xeon Processor 3400 Series Platform Diagram ..........10 ® 2-1 Intel Flex Memory Technology Operation..............22 2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes ....23 2-3 PCI Express* Layering Diagram .................
  • Page 6 Control Sideband and TAP Signal Group DC Specifications..........75 7-10 PCI Express* DC Specifications .................76 7-11 PECI DC Electrical Limits ..................77 ® ® Signals Not Used by the Intel Xeon Processor 3400 Series........79 Processor Pin List by Pin Name..................84 Datasheet, Volume 1...

  • Page 7: Revision History

    Revision History Revision Description Date Number September • Initial release 2009 January • Added workstation information 2010 • Added Intel Xeon X3480 processor June 2010 § § Datasheet, Volume 1...
  • Page 8 Datasheet, Volume 1...

  • Page 9: Introduction

    ® higher performance, easier validation, and improved x-y footprint. The Intel 3400 ® Series Chipset components for servers and workstations are the PCH. The Intel ® Xeon processor 3400 series is intended for UP server and workstation platforms. This document provides DC electrical specifications, signal integrity, differential...

  • Page 10: Intel Xeon Processor 3400 Series Platform Diagram

    PECI 6 Port s Serial ATA 3 Gb/ s Intel® Management USB 2.0 Engine Port s Intel® 3 400 Series Chipset Intel ® HD Audio SMBUS 2 .0 SPI Flash 8 x1 PCI Express* 2.0 Port s PCI Express* (2.5 GT/ s) Gigabit TPM 1.2...

  • Page 11: Processor Feature Details

    Some technologies may not be enabled on all processor SKUs. Refer to the processor specification update for details. ® Note: Intel Active Management Technology 6.0 is not supported on the Intel Xeon processor 3400 series for Intel 3400 and 3420 Chipset Platforms. Interfaces 1.2.1 System Memory Support ®...

  • Page 12: Pci Express

    ® • Intel Xeon processor 3400 series with the Intel 3420 Chipset supports: — One 16-lane PCI Express port intended for graphics or I/O. — Two 8-lane PCI Express ports intended for I/O. — Four 4-lane PCI Express ports intended for I/O.

  • Page 13: Direct Media Interface (Dmi)

    Introduction • PCI Express extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space. •...

  • Page 14: Platform Environment Control Interface (Peci)

    Memory Controller • Conditional self-refresh • Dynamic power-down 1.3.4 PCI Express* • L0s and L1 ASPM power management capability. ® — L0s not supported on the Intel Xeon processor 3400 series when configured as PCI Express 4x4 Datasheet, Volume 1...

  • Page 15: Thermal Management Support

    This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can, thus, help improve the overall security of the ® system. See the Intel 64 and IA-32 Architectures Software Developer's Manuals for more detailed information.
  • Page 16 Intel VT-d for enabling I/O device virtualization. VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d. Processor virtualization which when used in conjunction with Virtual Machine ® Intel...

  • Page 17: Related Documents

    Intel Xeon Processor 3400 Series and LGA1156 Socket Thermal and http://www.intel.com/Assets/PDF Mechanical Specifications and Design Guidelines /datasheet/322374.pdf ® ® Intel 5 Series Chipset and Intel 3400 Series Chipset Datasheet www.intel.com/Assets/PDF/datas heet/322169 ® ® www.intel.com/Assets/PDF/d Intel 5 Series Chipset and Intel 3400 Series Chipset Thermal and esignguide/322171.pdf...
  • Page 18 Introduction Datasheet, Volume 1...

  • Page 19: Interfaces

    — Raw Card D—Single Sided x8 unbuffered ECC — Raw Card E—Double Sided x8 unbuffered ECC • Intel 3400 and 3420 Chipset platforms DDR3 DIMM Modules — Raw Card D—Single Sided x8 unbuffered ECC — Raw Card E—Double Sided x8 unbuffered ECC —...

  • Page 20: Supported Dimm Module Configurations

    4 GB 2 Gb 256 M X 8 15/10 ® Intel 3400 and 3420 Chipset Platforms with Intel Xeon Processor 3400 Series SKUs: Registered/ECC Supported RDIMM Module Configurations and Unbuffered/ECC Supported DIMM Module Configurations (D and E) 1 GB 1 Gb...

  • Page 21: System Memory Timing Support

    Interfaces 2.1.2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface: • t = CAS Latency • t = Activate Command to READ or WRITE Command delay •...

  • Page 22: Dual-Channel Mode-Intel ® Flex Memory Technology Mode

    2.1.3.2 Dual-Channel Mode—Intel Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology mode. This mode combines the advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The...

  • Page 23: Rules For Populating Memory Slots

    This mode is used when Intel Flex Memory Technology is disabled and both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being different.

  • Page 24: Fma)

    ® (Intel FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.1 Just-in-Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next.

  • Page 25: Pci Express* Interface

    PCI Express Base Specification for details of PCI Express. The number of PCI Express controllers available is dependent on the platform: • Intel Xeon processor 3400 series with the Intel 3450 Chipset: 1 x16 PCI Express Graphics or 2x8 PCI Express Graphics are supported.

  • Page 26: Transaction Layer

    Interfaces packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-4. Packet Flow through the Layers 2.2.1.1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer.

  • Page 27: Pci Express* Configuration Mechanism

    Interfaces 2.2.2 PCI Express* Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-5. PCI Express* Related Register Structures in Processor PCI Express Port 0 Express* PCI-PCI PCI-PCI Device Bridge Bridge Compatible representing representing Host Bridge root PCI...

  • Page 28: Pci Express* Ports And Bifurcation

    Interfaces 2.2.3 PCI Express* Ports and Bifurcation The PCI Express interface on the processor is a single 16 lane (x16) port that can also be configured at narrower widths. It may be bifurcated (refer to Table 6-5) and each port may train to narrower widths. The PCI Express port is designed to be compliant with the PCI Express Base Specification rev 2.0 2.2.3.1 PCI Express* Bifurcated Mode...

  • Page 29: Platform Environment Control Interface (Peci)

    Interfaces Platform Environment Control Interface (PECI) The PECI is a one-wire interface that provides a communication channel between processor and a PECI master, usually the PCH. The processor implements a PECI interface to: • Allow communication of processor thermal and other information to the PECI master.
  • Page 30 Interfaces Datasheet, Volume 1...

  • Page 31: Technologies

    OSs and applications without any special steps. • Enhanced—Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. • More reliable—Due to the hardware support, VMMs can now be smaller, less complex, and more efficient.

  • Page 32: Intel Vt-D Objectives

    • Support for page-selective IOTLB invalidation • Support for queue-based invalidation interface • Support for Intel VT-d read prefetching/snarfing (such as, translations within a cacheline are stored in an internal buffer for reuse for subsequent transactions) • Support for ARI (Alternate Requester ID—a PCI SIG ECR for increasing the function...

  • Page 33: Intel Trusted Execution Technology (Intel Txt)

    Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute.

  • Page 34: Intel Hyper-Threading Technology

    Intel Turbo Boost Technology. BIOS and the operating system can enable or disable Intel Turbo Boost Technology. Note: Intel Turbo Boost Technology may not be available on all SKUs. Refer to the processor specification update for details. § §...

  • Page 35: Power Management

    Power Management Power Management This chapter provides information on the following power management topics: • ACPI States • Processor Core • IMC • PCI Express* ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States State...

  • Page 36: Pci Express* Link States

    Hard off Processor Core Power Management While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle.

  • Page 37: Enhanced Intel ® Speedstep ® Technology

    Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.

  • Page 38: Thread And Core C-State Entry And Exit

    Power Management Entry and exit of the C-States at the thread and core level are shown in Figure 4-2. Figure 4-2. Thread and Core C-State Entry and Exit MWAIT(C6), P_LVL3 I/O Read MWAIT(C 1), HLT MWAIT(C1), HLT (C1E Enabled) MWAIT(C3), P_LVL2 I/O Read While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved.

  • Page 39: Requesting Low-Power Idle States

    Power Management 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low-power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx.

  • Page 40: Core C0 State

    MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal ® state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads.

  • Page 41: Package C-States

    Power Management 4.2.5 Package C-States The processor supports C0, C1/C1E, C3, and C6 power states. The following is a summary of the general rules for package C-state entry. These apply to all package C- states unless specified otherwise: • A package C-state request is determined by the lowest numerical core C-state amongst all cores.

  • Page 42: Package C0

    Power Management Figure 4-3. Package C-State Entry and Exit 4.2.5.1 Package C0 The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state.

  • Page 43: Package C3 State

    Power Management 4.2.5.3 Package C3 State A processor enters the package C3 low power state when: • At least one core is in the C3 state. • The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform.

  • Page 44: Dram Power Management And Initialization

    Power Management 4.3.2 DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals, which the SDRAM controller supports. The processor drives four CKE pins to perform these operations.

  • Page 45: Dram I/O Power Management

    Power Management 4.3.2.4 DRAM I/O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference. This includes all signals associated with an unused memory channel. Clocks can be controlled on a per DIMM basis. Exceptions are made for per DIMM control signals, such as CS#, CKE, and ODT for unpopulated DIMM slots.
  • Page 46 Power Management Datasheet, Volume 1...

  • Page 47: Thermal Management

    Thermal Management Thermal Management For thermal specifications and design guidelines, refer to the appropriate Thermal and Mechanical Specifications and Design Guidelines (see Section 1.7). § § Datasheet, Volume 1...
  • Page 48 Thermal Management Datasheet, Volume 1...

  • Page 49: Signal Description

    Signaling Environment AC Specifications and are AC Coupled. The buffers are not 3.3 V tolerant. Refer to the PCI Express Specification. Intel Flexible Display Interface signals. These signals are compatible with PCI Express 2.0 Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3 V tolerant.

  • Page 50: System Memory Interface

    When activated during writes, the corresponding data SA_DM[7:0] groups in the SDRAM are masked. There is one SA_DM[7:0] for every data byte lane. Note: These signals are not used by the Intel Xeon processor 3400 series. They are connected to V on the package.

  • Page 51: Memory Channel B

    When activated during writes, the corresponding data groups in the SDRAM are masked. SB_DM[7:0] There is one SB_DM[7:0] for every data byte lane. Note: These signals are not used by the Intel Xeon processor 3400 series. They are connected to V on the package.

  • Page 52: Memory Reference And Compensation

    ® Intel Xeon processor 3400 series: 11 = 1 x16 PCI Express 10 = 2 x8 PCI Express 01 = 4 x4 PCI Express (requires Intel 3420 or 3400 Chipset) 00 = Reserved CMOS CFG[17:0] • CFG[2]: Reserved configuration land. A test point may be placed on the board for this land.

  • Page 53: Pci Express* Based Interface Signals

    This signal is connected to the PLTRST# output of the PCH. RESERVED. Must be left unconnected on the board. RSVD Intel does not recommend a test point on the board for this land. RESERVED/Non-Critical to Function: Pin for package RSVD_NCTF mechanical reliability.

  • Page 54: Pll Signals

    PEG_CLK Diff Clk This clock is used to generate the clocks necessary for PEG_CLK# the support of PCI Express. This also is the reference ® clock for Intel Flexible Display Interface. ® Intel Flexible Display Interface Signals Note: The signals noted below as not being used are included for reference to define all LGA 1156 land locations.

  • Page 55: Jtag/Itp Signals

    Signal Description JTAG/ITP Signals Table 6-10. JTAG/ITP Signal Name Description Direction Type Breakpoint and Performance Monitor Signals: Outputs from the processor that indicate the status of BPM#[7:0] breakpoints and programmable counters used for monitoring processor performance. DBR# is used only in systems where no debug port is implemented on the system board.

  • Page 56: Error And Thermal Protection

    Signal Description Error and Thermal Protection Table 6-11. Error and Thermal Protection Signal Name Description Direction Type Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.

  • Page 57: Power Sequencing

    Signal Description 6.10 Power Sequencing Table 6-12. Power Sequencing Signal Name Description Direction Type SKTOCC# (Socket Occupied): This signal will be pulled to ground on the processor package. There is no connection SKTOCC# to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present.
  • Page 58 Signal Description Table 6-13. Processor Core Power Signals (Sheet 2 of 2) Signal Name Description Direction Type VID[7:0] (Voltage ID) are used to support automatic selection of power supply voltages (V ). Refer to the Voltage Regulator-Down (VRD) 11.1 Design Guidelines for more information.

  • Page 59: Graphics And Memory Core Power Signals

    Signal Description 6.12 Graphics and Memory Core Power Signals Note: The signals noted below as not being used are included for reference to define all LGA 1156 land locations. These signals will be used by future processors that are compatible with LGA 1156 platforms. Table 6-14.

  • Page 60: Ground And Nctf

    Signal Description 6.13 Ground and NCTF Table 6-15. Ground and NCTF Signal Name Description Direction Type VSS are the ground pins for the processor and should be connected to the system ground plane. Corner Ground Connection: This land may be used to test for connection to ground.

  • Page 61: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Lands The processor has VCC, VTT, VDDQ, VCCPLL, VAXG, and VSS (ground) inputs for on- chip power distribution. All power lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane.

  • Page 62: Processor Clocking (Bclk[0], Bclk#[0])

    Electrical Specifications Processor Clocking (BCLK[0], BCLK#[0]) The processor uses a differential clock to generate the processor core(s) operating frequency, memory controller frequency, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by 133 MHz. Clock multiplying within the processor is provided by an internal phase locked loop (PLL) that requires a constant frequency input, with exceptions for Spread Spectrum Clocking (SSC).

  • Page 63: Vrd 11.1/11.0 Voltage Identification Definition

    Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 1 of 3) CC_MAX CC_MAX 1.04375 1.03750 1.60000 1.03125 1.59375 1.02500 1.58750 1.01875 1.58125 1.01250 1.57500 1.00625 1.56875 1.00000 1.56250 0.99375 1.55625 0.98750 1.55000 0.98125 1.54375 0.97500 1.53750 0.96875 1.53125 0.96250 1.52500 0.95626...
  • Page 64 Electrical Specifications Table 7-1. VRD 11.1/11.0 Voltage Identification Definition (Sheet 2 of 3) CC_MAX CC_MAX 1.36875 0.80000 1.36250 0.79375 1.35625 0.78750 1.35000 0.78125 1.34375 0.77500 1.33750 0.76875 1.33125 0.76250 1.32500 0.75625 1.31875 0.75000 1.31250 0.74375 1.30625 0.73750 1.30000 0.73125 1.29375 0.72500 1.28750 0.71875...

  • Page 65: Market Segment Selection Truth Table For Msid[2:0]

    The MSID[2:0] signals are provided to indicate the maximum platform capability to the processor. ® 2009A processors have thermal requirements that are equivalent to those of the Intel Core™2 Duo E8000 processor series. Refer to the appropriate processor Thermal and Mechanical Specifications and Design...

  • Page 66: Reserved Or Unused Signals

    Electrical Specifications Reserved or Unused Signals The following are the general types of reserved (RSVD) signals and connection guidelines: • RSVD – these signals should not be connected • RSVD_TP – these signals should be routed to a test point •...

  • Page 67: Signal Groups 1

    Electrical Specifications Table 7-3. Signal Groups (Sheet 1 of 2) Alpha Signal Group Type Signals Group System Reference Clock BCLK[0], BCLK#[0], Differential CMOS Input BCLK[1], BCLK#[1], PEG_CLK, PEG_CLK# Differential CMOS Output BCLK_ITP, BCLK_ITP# DDR3 Reference Clocks SA_CK[3:0], SA_CK#[3:0] Differential DDR3 Output SB_CK[3:0], SB_CK#[3:0] DDR3 Command Signals SA_RAS#, SB_RAS#,...
  • Page 68 SA and SB refer to DDR3 Channel A and DDR3 Channel B. These signals are only used on processors and platforms that support ECC DIMMs. These signals will not be actively used on the Intel Xeon processor 3400 series. All Control Sideband Asynchronous signals are required to be asserted/de-asserted for at least eight BCLKs for the processor to recognize the proper signal state.

  • Page 69: Test Access Port (Tap) Connection

    Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.

  • Page 70: Dc Specifications

    VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M...

  • Page 71: Processor Uncore I/O Buffer Supply Dc Voltage And Current Specifications

    1.575 DDR3 PLL supply voltage (DC + AC 1.71 1.89 CCPLL specification) Intel Xeon processor 3400 series with 95 W TDP: Current for the — — memory controller and Shared Cache Intel Xeon processor 3400 series with 45 W TDP: Current for the —...

  • Page 72: Static And Transient Tolerance

    Electrical Specifications Table 7-7. Static and Transient Tolerance 1, 2, 3 Voltage Deviation from VID Setting CC_Max CC_Typ CC_Min 1.40 m 1.40 m 1.40 m 0.000 -0.019 -0.038 -0.007 -0.026 -0.045 -0.014 -0.033 -0.052 -0.021 -0.040 -0.059 -0.028 -0.047 -0.066 -0.035 -0.054 -0.073...

  • Page 73: Vcc Static And Transient Tolerance Loadlines

    Electrical Specifications Figure 7-1. Static and Transient Tolerance Loadlines Icc [A] VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 VID - 0.050 VID - 0.063 Vcc Maximum VID - 0.075 VID - 0.088 VID - 0.100 VID - 0.113 Vcc Minimum VID - 0.125...

  • Page 74: Ddr3 Signal Group Dc Specifications

    Electrical Specifications Table 7-8. DDR3 Signal Group DC Specifications Alpha Symbol Parameter Units Notes Group Input Low Voltage (e,f) — — 0.43*V Input High Voltage (e,f) 0.57*V — — Output Low Voltage / 2)* (R (c,d,e,f) — — VTT_TERM Output High Voltage –...

  • Page 75: Control Sideband And Tap Signal Group Dc Specifications

    Electrical Specifications Table 7-9. Control Sideband and TAP Signal Group DC Specifications Symbol Alpha Group Parameter Units Notes (m),(n),(p),(qa),(qb),(s) Input Low Voltage — — 0.64 (m),(n),(p),(qa),(qb),(s) Input High Voltage 0.76 — — Input Low Voltage — — 0.40 Input High Voltage 0.75 —...

  • Page 76: Pci Express* Dc Specifications

    Electrical Specifications Table 7-10. PCI Express* DC Specifications Alpha Symbol Parameter Units Notes Group (ad) Differential peak to peak Tx TX-DIFF-p-p — voltage swing (ad) Tx AC Peak Common Mode TX_CM-AC-p — — 1,2,6 Output Voltage (Gen1 only) (ad) Tx AC Peak-to-Peak Common TX_CM-AC-p-p Mode Output Voltage (Gen2 —...

  • Page 77: Platform Environmental Control Interface (Peci) Dc Specifications

    Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

  • Page 78: Input Device Hysteresis

    Electrical Specifications 7.10.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design. Figure 7-2. Input Device Hysteresis Maximum V PECI High Range Minimum V...

  • Page 79: Processor Land And Signal Information

    Not all signals are used by the processor. Table 8-1 lists the signals that are not used by the Intel Xeon processor 3400 series. ® ® Table 8-1.

  • Page 80: Socket Pinmap (Top View, Upper-Left Quadrant)

    Processor Land and Signal Information Figure 8-1. Socket Pinmap (Top View, Upper-Left Quadrant) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDDQ VDDQ RSVD_NCTF SA_DQ[49] SA_DQ[52] SB_CS#[0] SB_MA[10] SA_ODT[3] SB_CAS# SB_RAS#...

  • Page 81: Socket Pinmap (Top View, Upper-Right Quadrant)

    Processor Land and Signal Information Figure 8-2. Socket Pinmap (Top View, Upper-Right Quadrant) 20 19 18 17 16 15 14 13 12 11 10 VDDQ VDDQ VDDQ SB_MA[4] SB_MA[9] SA_MA[1] SA_MA[5] SB_MA[14] SA_CKE[3] SB_CKE[1] SA_DQ[27] SA_DQS[3] SA_DQ[25] RSVD_NCTF VDDQ SA_MA[0] SB_MA[6] SB_MA[11] SB_MA[12]...

  • Page 82: Socket Pinmap (Top View, Lower-Left Quadrant)

    Processor Land and Signal Information Figure 8-3. Socket Pinmap (Top View, Lower-Left Quadrant) VTT VTT VTT VTT VTT VTT VSS VSS VSS VSS VSS VSS V VTT VTT VTT VTT VTT VTT VTT VTT VID[6] VID[7] VID[0]/MSID[0] VID[1]/MSID[1] VID[2]/MSID[2] VID[3]/CSC[0] VID[4]/CSC[1] VID[5]/CSC[2] VSS VSS VSS VSS...

  • Page 83: Socket Pinmap (Top View, Lower-Right Quadrant)

    Processor Land and Signal Information Figure 8-4. Socket Pinmap (Top View, Lower-Right Quadrant) BCLK#[1] FDI_TX[7] FDI_TX#[7] FDI_TX[6] FDI_TX#[6] VTT W FDI_TX[3] FDI_TX[4] FDI_TX#[3] FDI_TX#[4] DMI_RX[3] DMI_RX#[3] VTT VTT VTT FDI_TX[1] FDI_TX#[1] DMI_RX#[2] FDI_TX[2] FDI_TX#[2] FDI_TX[0] FDI_TX#[0] DMI_RX[1] DMI_RX#[1] DMI_RX[2] VTT VTT VTT PEG_RX#[15] PEG_RX[15] DMI_RX#[0]...

  • Page 84: Processor Pin List By Pin Name

    Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Name Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. DMI_RX[2] BCLK_ITP AK39 CMOS DMI_RX[3] BCLK_ITP# AK40 CMOS...
  • Page 85 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. GFX_VID[5] CMOS PEG_TX[1] PCI Express GFX_VID[6] CMOS PEG_TX[10]...
  • Page 86 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. RSVD AJ39 RSVD_NCTF AY37 RSVD AK12 RSVD_NCTF RSVD...
  • Page 87 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SA_DQ[15] DDR3 SA_DQ[55] AW37 DDR3 SA_DQ[16] DDR3 SA_DQ[56]...
  • Page 88 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SA_MA[13] AU24 DDR3 SB_DM[3] DDR3 SA_MA[14] AT11 DDR3...
  • Page 89 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. SB_DQ[44] AT31 DDR3 SB_ECC_CB[1] AT13 DDR3 SB_DQ[45] AR31...
  • Page 90 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG...
  • Page 91 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. Datasheet, Volume 1...
  • Page 92 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. VCC_NCTF VCC_NCTF VCC_SENSE Analog VCCPLL VCCPLL VCCPLL VCCPWRGOOD_0...
  • Page 93 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. VID[5]/CSC[2] CMOS AJ26 VID[6] CMOS AJ28 VID[7] CMOS...
  • Page 94 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. AP24 AP26 AP27 AP29 AP33 AP35 AP38 AR20...
  • Page 95 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. Datasheet, Volume 1...
  • Page 96 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Table 8-2. Processor Pin List by Pin Name Name Pin Name Pin # Buffer Type Dir. Pin Name Pin # Buffer Type Dir. AD40 AE33 AE34 AE39 AE40 AF33 AG33 AJ17...
  • Page 97 Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VTT_SELECT AF39 CMOS VTT_SENSE AE35 Analog VTTPWRGOOD AG37 Asynch CMOS § § Datasheet, Volume 1...
  • Page 98 Processor Land and Signal Information Datasheet, Volume 1...

This manual is also suitable for:

Bv80605001914ag - processor - 1 x xeon x3430Bx80605x3440 - quad core xeon x3440Xeon 3400 series

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