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Status:
For the steppings affected, see the Summary Tables of Changes.
16.
IA32_MC0_STATUS Register Overflow Bit Not Set Correctly
Problem:
The Overflow Error bit (bit 62) in the IA32_MC0_STATUS register indicates, when set,
that a machine check error occurred while the results of a previous error were still in
the error reporting bank (i.e. the valid bit was set when the new error occurred). In
the case of this erratum, if an uncorrectable error is logged in the error-reporting
bank and another error occurs, the overflow bit will not be set.
Implication: When this erratum occurs the overflow bit will not be set.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
17.
Performance Counter May Contain Incorrect Value after Being
Stopped
Problem:
If a performance counter is stopped on the precise internal clock cycle where the
intermediate carry from the lower 32 bits of the counter to the upper eight bits
occurs, the intermediate carry is lost.
Implication: When this erratum occurs, the performance counter will contain a value about 4
billion (2
Workaround:
Since this erratum does not occur if the performance counters are read when
running, a possible workaround is to read the counter before stopping it. Since the
lower 32 bits will always be correct, event counting which does not exceed 2
will not be affected.
Status:
For the steppings affected, see the Summary Tables of Changes.
18.
The TAP Drops the Last Bit during Instruction Register Shifting
Problem:
While shifting in new opcode bits during the Shift-IR state, the test access port (TAP)
should shift out, via the TDO pin, a 1 followed by enough 0s to fill up the rest of the
opcode length. Since the processor TAP has 7 opcode bits, it should shift out
0000001. The TAP stops driving on the same TAP clock edge that the receiver
samples, with the result that 0000001 or 1000001 might be observed.
Implication: The last bit may be incorrect during instruction register shifting.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
19.
Data Breakpoints on the High Half of a Floating Point Line Split May
Not Be Captured
Problem:
When a floating point load which splits a 64-byte cache line gets a floating point stack
fault, and a data breakpoint register maps to the high line of the floating point load,
36
32
) less than it should.
Errata
32
events
Specification Update
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