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No.
B2
C1
D0
N39
X
X
X
N40
X
X
X
N41
X
N42
X
X
X
N43
X
X
X
N44
X
X
X
N45
X
X
N46
X
X
N47
X
X
N48
X
X
X
N49
X
X
X
N50
X
X
X
N51
X
X
N52
X
X
X
N53
X
X
X
N54
X
X
X
N55
X
X
X
16
E0
B0
C1
D1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Summary Tables of Changes
M0
Plan
as expected
Processor may Timeout Waiting for a
Fixed
Device to Respond after ~0.67 Seconds
Cascading of Performance Counters
X
No Fix
does not work Correctly when Forced
Overflow is Enabled
Possible Machine Check Due to Line-
Fixed
Split Loads with Page-Tables in
Uncacheable (UC) Space
IA32_MC1_STATUS MSR ADDRESS
Fixed
VALID bit may be set when no Valid
Address is Available
EMON event counting of x87 loads may
X
No Fix
not work as expected
Software controlled clock modulation
Fixed
using a 12.5% or 25% duty cycle may
cause the processor to hang
Speculative page fault may cause
Fixed
livelock
PAT index MSB may be calculated
Fixed
incorrectly
SQRTPD and SQRTSD may return
Fixed
QNaN indefinite instead of negative
zero
Bus invalidate line requests that return
Fixed
unexpected data may result in L1
cache corruption
Write Combining (WC) load may result
Fixed
in unintended address on system bus
Incorrect data may be returned when
Fixed
page tables are in Write Combining
(WC) memory space
Buffer on resistance may exceed
Fixed
specification
Processor issues inconsistent
X
No Fix
transaction size attributes for locked
operation
Multiple accesses to the same S-state
L2 cache line and ECC error
Fixed
combination may result in loss of cache
coherency
Processor may hang when resuming
Fixed
from Deep Sleep state
When the processor is in the System
X
No Fix
Management Mode (SMM), debug
registers may be fully writeable
ERRATA
Specification Update
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