Table of Contents
Advertisement
Errata
79.
Simultaneous Page Faults at Similar Page Offsets on Both Logical
Processors of a Hyper-Threading Technology Enabled Processor May
Cause Application Failure
Problem:
An incorrect value of CR2 may be presented to one of the logical processors of an HT
Technology enabled processor if a page access fault is encountered on one logical
processor in the same clock cycle that the other logical processor also encounters a
page fault. Both accesses must cross the same 4 byte aligned offset for this erratum
to occur. Only a small percentage of such simultaneous accesses are vulnerable. The
vulnerability of the alignment for any given fault is dependent on the state of other
circuitry in the processor.
sequentially after one of these simultaneous faults has to be pending at the time of
the simultaneous faults. This erratum is caused by a one-cycle hole in the logic that
controls the timing by which a logical processor is allowed to access an internal
asynchronous fault address register. The end result is that the value of CR2
presented to one logical processor may be corrupted.
Implication: The operating system is likely to terminate the application that generated an
incorrect value of CR2.
Workaround:
An operating system or page management software can significantly reduce the
already small possibility of encountering this failure by restarting or retrying the
faulting instruction and only terminate the application on a subsequent failure of the
same instruction. It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
80.
System Bus Interrupt Messages without Data Which Receive a
HardFailure Response May Hang the Processor
Problem:
When a system bus agent (processor or chipset) issues an interrupt transaction
without data onto the system bus and the transaction receives a HardFailure
response, a potential processor hang can occur. The processor, which generates an
inter-processor interrupt (IPI) that receives the HardFailure response, will still log the
MCA error event cause as HardFailure, even if the APIC causes a hang. Other
processors, which are true targets of the IPI, will also hang on hardfail-without-data,
but will not record an MCA HardFailure event as the cause. If a HardFailure response
occurs on a system bus interrupt message with data, the APIC will complete the
operation so as not to hang the processor.
Implication: The processor may hang.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
81.
Memory Type of the Load Lock Different from Its Corresponding
Store Unlock
Problem:
A use-once protocol is employed to ensure that the processor in a multi-agent
system may access data that is loaded into its cache on a Read-for-Ownership
operation at least once before it is snooped out by another agent. This protocol is
Specification Update
Additionally, a third fault from an access that occurs
59
Advertisement
Table of Contents
