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Errata
54.
Processor May Hang When Resuming from Deep Sleep State
Problem:
When resuming from the Deep Sleep state the address strobe signals (ADSTB
[1:0]#) may become out of phase with respect to the system bus clock (BCLK).
Implication: When this erratum occurs, the processor will hang.
Workaround:
The system BIOS should prevent the processor from going to the Deep Sleep
state.
Status:
For the steppings affected, see the Summary Tables of Changes.
55.
When the Processor Is in the System Management Mode (SMM),
Debug Registers May Be Fully Writeable
Problem:
When in System Management Mode (SMM), the processor executes code and stores
data in the SMRAM space. When the processor is in this mode and writes are made to
DR6 and DR7, the processor should block writes to the reserved bit locations. Due to
this erratum, the processor may not block these writes. This may result in invalid
data in the reserved bit locations.
Implication: Reserved bit locations within DR6 and DR7 may become invalid.
Workaround:
Software may perform a read/modify/write when writing to DR6 and DR7 to
ensure that the values in the reserved bits are maintained.
Status:
For the steppings affected, see the Summary Tables of Changes.
56.
Associated Counting Logic Must Be Configured When Using Event
Selection Control (ESCR) MSR
Problem:
ESCR MSRs allow software to select specific events to be counted, with each ESCR
usually associated with a pair of performance counters. ESCRs may also be used to
qualify the detection of at-retirement events that support precise-event-based
sampling (PEBS). A number of performance metrics that support PEBS require a 2nd
ESCR to tag uops for the qualification of at-retirement events. (The first ESCR is
required to program the at-retirement event.) Counting is enabled via counter
configuration control registers (CCCR) while the event count is read from one of the
associated counters. When counting logic is configured for the subset of at-
retirement events that require a second ESCR to tag uops, at least one of the CCCRs
in the same group of the second ESCR must be enabled.
Implication: If no CCCR/counter is enabled in a given group, the ESCR in that group that is
programmed for tagging uops will have no effect. Hence a subset of performance
metrics that require a second ESCR for tagging uops may result in 0 count.
Workaround:
Ensure that at least one CCCR/counter in the same group as the tagging ESCR is
enabled for those performance metrics that require two ESCRs and tagging uops for
at-retirement counting.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
51
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