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76.
Changes to CR3 Register Do Not Fence Pending Instruction Page
Walks
Problem:
When software writes to the CR3 register, it is expected that all previous/outstanding
code, data accesses and page walks are completed using the previous value in CR3
register. Due to this erratum, it is possible that a pending instruction page walk is still
in progress, resulting in an access (to the PDE portion of the page table) that may be
directed to an incorrect memory address.
Implication: The results of the access to the PDE will not be consumed by the processor so the
return of incorrect data is benign. However, the system may hang if the access to the
PDE does not complete with data (e.g. infinite number of retries).
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
77.
The State of the Resume Flag (RF Flag) in a Task-State Segment
(TSS) May Be Incorrect
Problem:
After executing a JMP instruction to the next (or other) task through a hardware task
switch, it is possible for the state of the RF flag (in the EFLAGS register image) to be
incorrect.
Implication: The RF flag is normally used for code breakpoint management during debug of an
application. It is not typically used during normal program execution. Code
breakpoints or single step debug behavior in the presence of hardware task switches,
therefore, may be unpredictable as a result of this erratum. This erratum has not
been observed in commercially available software.
Workaround:
None.
Status:
For the steppings affected, see the Summary Tables of Changes.
78.
Processor Provides a 4-Byte Store Unlock after an 8-Byte Load Lock
Problem:
When the processor is in the Page Address Extension (PAE) mode and detects the
need to set the Access and/or Dirty bits in the page directory or page table entries,
the processor sends an 8 byte load lock onto the system bus. A subsequent 8 byte
store unlock is expected, but instead a 4 byte store unlock occurs. Correct data is
provided since only the lower bytes change, however external logic monitoring the
data transfer may be expecting an 8 byte load lock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround:
None identified at this time.
Status:
For the steppings affected, see the Summary Tables of Changes.
58
Errata
Specification Update
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