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Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
63.
Re-Mapping the APIC Base Address to a Value Less Than or Equal to
0xDC001000 May Cause IO and Special Cycle Failure
Problem:
Remapping the APIC base address from its default can cause conflicts with either I/O
or special cycle bus transactions.
Implication: Either I/O or special cycle bus transactions can be redirected to the APIC, instead of
appearing on the front-side bus.
Workaround:
Use any APIC base addresses above 0xDC001000 as the relocation address.
Status:
For the steppings affected, see the Summary Tables of Changes.
64.
Erroneous BIST Result Found in EAX Register after Reset
Problem:
The processor may show an erroneous BIST (built-in self test) result in the EAX
register bit 0 after coming out of reset.
Implication: When this erratum occurs, an erroneous BIST failure will be reported in the EAX
register bit 0, however this failure can be ignored since it is not accurate.
Workaround:
It is possible for BIOS to workaround this issue by masking off bit 0 in the EAX
register where BIST results are written.
Status:
For the steppings affected, see the Summary Tables of Changes.
65.
Processor Does Not Flag #GP on Non-Zero Write to Certain MSRs
Problem:
When a non-zero write occurs to the upper 32 bits of IA32_CR_SYSENTER_EIP or
IA32_CR_SYSENTER_ESP, the processor should indicate a general protection fault by
flagging #GP. Due to this erratum, the processor does not flag #GP.
Implication: The processor unexpectedly does not flag #GP on a non-zero write to the upper 32
bits of IA32_CR_SYSENTER_EIP or IA32_CR_SYSENTER_ESP. No known commercially
available operating system has been identified to be affected by this erratum.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
66.
Simultaneous Assertion of A20M# and INIT# May Result in Incorrect
Data Fetch
Problem:
If A20M# and INIT# are simultaneously asserted by software, followed by a data
access to the 0xFFFFFXXX memory region, with A20M# still asserted, incorrect data
will be accessed. With A20M# asserted, an access to 0xFFFFFXXX should result in a
load from physical address 0xFFEFFXXX. However, in the case of A20M# and INIT#
being asserted together, the data load will actually be from the physical address
0xFFFFFXXX. Code accesses are not affected by this erratum.
54
Errata
Specification Update
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