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Errata
Problem:
The processor may incorrectly go to the Machine Check handler in the following
scenario:
• Error reporting is enabled in the IA32_MC1_CTL register,
• The processor issues a Read for Ownership (RFO) that hits an L2 cache line in the
Shared state, and
• This RFO access also receives a correctable error.
• An external snoop hits the same cacheline immediately after the RFO.
Implication: When this erratum occurs, the processor will incorrectly enter the machine check
handler. A correctable error will also be reported in the IA32_MC1_STATUS and
IA32_MC0_STATUS registers. This erratum has only been observed in a focused
testing environment.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
34.
Processor May Report Invalid TSS Fault Instead of Double Fault
during Mode C Paging
Problem:
When an operating system executes a task switch via a Task State Segment (TSS)
the CR3 register is always updated from the new task TSS. In the mode C paging,
once the CR3 is changed the processor will attempt to load the PDPTRs. If the CR3
from the target task TSS or task switch handler TSS is not valid then the new PDPTR
will not be loaded. This will lead to the reporting of invalid TSS fault instead of the
expected Double fault.
Implication: Operating systems that access an invalid TSS may get invalid TSS fault instead of a
Double fault.
Workaround:
Software needs to ensure any accessed TSS is valid.
Status:
For the steppings affected, see the Summary Tables of Changes.
35.
IA32_MC0_STATUS Incorrect after Illegal APIC Request
Problem:
When an invalid APIC access error is logged in the IA32_MC0_STATUS register, the
value returned should indicate a complex bus and interconnect error but instead
indicates a complex memory hierarchy error.
Implication: When this erratum occurs, the IA32_MC0_STATUS register will contain incorrect
information.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
36.
Thermal Status Log Bit May Not Be Set When the Thermal Control
Circuit Is Active
Specification Update
41
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