Table of Contents
Advertisement
Processor DCU Prefetcher
The Data Cache Unit (DCU) prefetcher detects multiple readings from a single
cache line for a determined period of time. It then loads the following line in the
L1 cache; and one for each core too.
The hardware prefetch mechanisms are efficient, and in practice can increase
the success rate of the cache subsystem. However, the prefetch can also have
the opposite result. Frequent errors tend to pollute cache with useless data,
reducing its success rate. This is why you may deactivate most of the hardware
prefetch mechanisms. Intel recommends deactivating the DCU prefetch in
processors that are intended for servers, because it can reduce performances in
some applications.
Note: In the BIOS, all four prefetchers are disabled by default. Most
benchmarks in the performance lab indicate that this combination offers the
best performance because many benchmarks typically have very high CPU
and FSB utilization rates. Prefetching adds extra overhead, often slowly in a
very busy system.
However, try all combinations of these prefetchers on their specific workload;
in many cases, other combinations help. Systems not running at high CPU
and FSB utilizations might find prefetching beneficial.
C1E
This setting allows you to enable (by default) or disable the Enhanced Halt State
(C1E).
If the Enhanced Halt State is enabled, the operating system allows the processor
to alter the core frequency after sending an idle command such as HALT or
MWAIT. The processor core speed slows down and then transitions to the lower
voltage.
Enhanced Halt State is a low power state entered when all processor cores have
executed the HALT or MWAIT instructions and Extended HALT state has been
enabled. When one of the processor cores executes the HALT instruction, that
processor core is halted; however, the other processor cores continue normal
operation. The processor automatically transitions to a lower core frequency and
voltage operating point before entering the Extended HALT state.
110
Planning, Installing, and Managing the IBM System x3950 M2
Advertisement
Table of Contents
