Omron CPM2C Operation Manual page 60

Specifications
Item
Programming language
Instruction length
Instructions
Execution time
Program capacity
Max. I/O CPU Unit only
capacity
With Expansion
I/O Units and
Expansion Units
Input bits
Output bits
Work bits
Special bits (SR area)
Temporary bits (TR area)
Holding bits (HR area)
Auxiliary bits (AR area)
Link bits (LR area)
Timers/Counters
Data memory
Interrupt processing
Interval timer interrupts
High-speed counter
Interrupt Inputs
(Counter mode)
Pulse output
Synchronized pulse control One point:
Quick-response inputs
Input time constant
(ON response time =
OFF response time)
10 I/O points
(relay/transistor outputs)
Ladder diagram
1 step per instruction, 1 to 5 words per instruction
Basic instructions: 14
Special instructions: 105 instructions, 185 variations
0.64 µs (LD instruction)
Basic instructions:
7.8 µs (MOV instruction)
Special instructions:
4,096 words
10 points
170 points max.
IR 00000 to IR 00915 (Words not used for input bits can be used for work bits.)
IR 01000 to IR 01915 (Words not used for output bits can be used for work bits.)
928 bits: IR 02000 to IR 04915 and IR 20000 to IR 22715
448 bits: SR 22800 to SR 25515
8 bits (TR0 to TR7)
320 bits: HR 0000 to HR 1915 (Words HR 00 to HR 19)
384 bits: AR 0000 to AR 2315 (Words AR 00 to AR 23)
256 bits: LR 0000 to LR 1515 (Words LR 00 to LR 15)
256 timers/counters (TIM/CNT 000 to TIM/CNT 255)
1-ms timers: TMHH(−−)
10-ms timers: TIMH(15)
100-ms timers: TIM
1-s/10-s timers: TIML(−−)
Decrementing counters: CNT
Reversible counters: CNTR(12)
Read/Write: 2,048 words (DM 0000 to DM 2047)*
Read-only: 456 words (DM 6144 to DM 6599)
PC Setup: 56 words (DM 6600 to DM 6655)
*The Error Log is contained in DM 2000 to DM 2021.
2 interrupts
Shared by the external interrupt inputs (counter mode) and the quick-response inputs.
1 (Scheduled Interrupt Mode or Single Interrupt Mode)
One high-speed counter: 20 kHz single-phase or 5 kHz two-phase (linear count method)
Counter interrupt: 1 (set value comparison or set-value range comparison)
2 inputs
Shared by the external interrupt inputs and the quick-response inputs.
Two points with no acceleration/deceleration, 10 Hz to 10 kHz each, and no direction control.
One point with trapezoid acceleration/deceleration, 10 Hz to 10 kHz, and direction control.
Two points with variable duty-ratio outputs.
(Pulse outputs can be used with transistor outputs only, they cannot be used with relay out-
puts.)
A pulse output can be created by combining the high-speed counter with pulse outputs and
multiplying the frequency of the input pulses from the high-speed counter by a fixed factor.
(This output is possible with transistor outputs only, it cannot be used with relay outputs.)
2 inputs
Shared by the external interrupt inputs and the interrupt inputs (counter mode).
Min. input pulse width: 50 µs max.
Can be set for all input points.
(1 ms, 2 ms, 3 ms, 5 ms, 10 ms, 20 ms, 40 ms, or 80 ms)
CPU Unit Specification
20 I/O points
(relay/transistor outputs)
20 points
180 points max.
4 interrupts
4 inputs
4 inputs
Section 2-1
32 I/O points
(transistor outputs)
32 points
192 points max.
4 interrupts
4 inputs
4 inputs
37