Page 1 Cat. No. W353-E1-06 SYSMAC CPM1/CPM1A/CPM2A/CPM2C/SRM1(-V2) Programmable Controllers PROGRAMMING MANUAL...
Page 2 CPM1/CPM1A/CPM2A/CPM2C/SRM1(-V2) Programmable Controllers Programming Manual Revised February 2008...
Page 4 1. Indicates lists of one sort or another, such as procedures, checklists, etc. OMRON, 1999 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permis- sion of OMRON.
Page 6: Table Of Contents
2-11 CompoBus/S I/O Slave Functions (CPM1A/CPM2A/CPM2C Only) ....2-12 CompoBus/S I/O Master Functions (SRM1(-V2) and CPM2C-S Only) ....
Page 7 ............7-11 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) .
Page 8 ........... . B Error and Arithmetic Flag Operation .
Page 10 Please read this manual carefully and be sure you understand the information provided before attempting to program or operate the PC. Section 1 explains the PC Setup. The PC Setup can be used to control the operating parameters. Section 2 explains special features of the PC.
Page 11 About this Manual, Continued Section 4 describes how to use the communications functions provided in the PCs. Section 5 describes the structure of the PC memory areas and explains how to use them. Details of some areas are provided in Appendix C.
Page 12 Warranty and Limitations of Liability Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á WARRANTY Á...
Page 13 Application Considerations Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á SUITABILITY FOR USE Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 14 Disclaimers Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á CHANGE IN SPECIFICATIONS Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á...
Page 16 This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the Programmable Con- troller. You must read this section and understand the information contained before attempting to set up or operate a PC system.
Page 17: Intended Audience
WARNING It is extremely important that a PC and all PC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PC System to the above-mentioned applications.
Page 18 When connecting the PC to a personal computer or other peripheral device, either ground the 0-V side of the PC or do not ground the PC at all. Although some grounding methods short the 24-V side, as shown in the following dia- gram, never do so with the PC.
Page 19: Operating Environment Precautions
Locations close to power supplies. Caution The operating environment of the PC System can have a large effect on the lon- gevity and reliability of the system. Improper operating environments can lead to malfunction, failure, and other unforeseeable problems with the PC System. Be sure that the operating environment is within the specified conditions at installa- tion and remains within the specified conditions during the life of the system.
Page 20: Application Precautions
Install the Units properly as specified in the relevant operation manual(s). Im- proper installation of the Units may result in malfunction. Do not install the PC or PC Units in places where the Units may be affected by excessive noise. Doing so may result in malfunction.
Page 21 Be particularly careful in places where the power supply is unstable. Do not apply voltages to the input terminals in excess of the rated input voltage. Excess voltages may result in burning. Do not apply voltages or connect loads to the output terminals in excess of the maximum switching capacity.
Page 22 Maintenance When replacing a part, be sure to confirm that the rating of a new part is correct. Not doing so may result in malfunction or burning. When the CPU Unit is replaced, resume operation only after transferring to the new CPU Unit the contents of the DM and HR Areas required for operation.
Page 23 Start Guide (W332) and User Manual (W333) for SYSMAC-CPT Support Software procedures. If you are not familiar with OMRON PCs or ladder diagram program, you can read 1-1 PC Setup as an overview of the operat- ing parameters available for the CPM1/CPM1A, CPM2A/CPM2C, and SRM1(-V2). You may then want to read Section 5 Memory Areas, Section 6 Ladder-diagram Programming, and related instructions in Section 7 Instruction Set before complet- ing this section.
Page 24: Pc Setup
Since changes in the PC Setup become effective only at the times given above, the PC will have to be restarted to make changes in DM 6600 to DM 6614 effec- tive, and program execution will have to be restarted to make changes in DM 6615 to DM 6644 effective.
Page 25: Cpm1/Cpm1A Pc Setup Settings
DM 6604 00 to 07 00: If data could not be saved with the built-in capacitor (AR 1314 ON), a memory error will not be generated. 01: If data could not be saved with the built-in capacitor (AR 1314 ON), a memory error will be generated.
Page 26 00 to 03 Input constant for IR 00000 to IR 00002 0: 8 ms; 1: 1 ms; 2: 2 ms; 3: 4 ms; 4: 8 ms; 5: 16 ms; 6: 32 ms; 7: 64 ms; 8: 128 ms 04 to 07...
Page 27 DM 6651 00 to 07 Baud rate 00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K, 05 to 07: Cannot be used (see note (Other settings will cause a non-fatal error and AR 1302 will turn ON.) 08 to 15...
Page 28 PC Setup Section 2. Do not set to “05” to “07.” If set to this value, the CPM1/CPM1A will not oper- ate properly and the RUN PC Setup Error Flag (AR 1302 ON) will not turn 3. Retention of IOM Hold Bit (SR 25212) Status If the “IOM Hold Bit Status at Startup”...
Page 29: Cpm2A/Cpm2C Pc Setup Settings
DM 6614 Note For CPM2C PCs with lot number of 3180O or earlier, the startup operating mode will be as shown in the following table if bits 08 to 15 of DM 6600 are set to 00. Communications port setting switch...
Page 30 00 to 03 Input time constant for IR 00000 to IR 00002 0: 10 ms; 1: 1 ms; 2: 2 ms; 3: 3 ms; 4: 5 ms; 5: 10 ms; 6: 20 ms; 7: 40 ms; 8: 80 ms 04 to 07...
Page 31 (all 0) regardless of the settings in DM 6645 through DM 6649. If pin 2 of the CPM2C CPU Unit’s DIP switch is ON, communications through the CPM2C’s RS-232C port are governed by the default settings (all 0) regardless of the settings in DM 6645 through DM 6649.
Page 32 12 to 15 End code selection for no-protocol communications 0: Disables end code; 1: Enables end code in DM 6649; 2: Sets end code of CR, LF. (Any other setting disables the end code, causes a non-fatal error, and turns ON AR 1302.)
Page 33 Support Software set for peripheral bus communications. The CPM2A CPU Unit will auto-detect either Programming Device and automatically establish communications. SW2 on the CPM2C CPU Unit must be OFF in order for communications through the CPM2C’s peripheral port to be gov- erned by the settings in DM 6650 through DM 6654.
Page 34 Low battery error detection is disabled (i.e., set to 1) by default in CPU Units that do not have a clock. If the PC Setup is cleared, the setting will changed to 0 and a low battery error will occur.
Page 35: Srm1(-V2) Pc Setup Settings
DM 6604 00 to 07 00: If data could not be saved for a power interruption (AR 1314 ON), a memory error will not be generated. 01: If data could not be saved for a power interruption (AR 1314 ON), a memory error will be generated.
Page 36 12 to 15 Communications mode 0: Host Link; 1: No-protocol; 2: 1:1 PC Link Slave; 3: 1:1 PC Link Master; 4: 1:1 NT Link; 5: 1:N NT Link (Any other setting specifies Host Link mode, causes a non-fatal error, and turns ON AR 1302.)
Page 37 Other: 1 bit 7 bits 2 bits Even AR 1302 will turn ON to indicate a non-fatal system setting error if any value not be- tween 00 and 11 is set. DM 6652 00 to 15 Transmission delay (Host Link) 0000 to 9999 (BCD): Set in units of 10 ms.
Page 38: Basic Pc Operation And I/O Processes
This section explains the PC Setup settings related to basic operation and I/O processes. 1-2-1 Startup Mode The operation mode the PC will start in when power is turned on can be set as shown below. DM6600 Startup Mode Designation...
Page 39: Hold Bit Status
In CPM1, CPM1A, CPM2A, and CPM2C PCs, the program memory can be pro- tected by setting bits 00 to 03 of DM 6602 to 1. Bits 04 to 07 determine whether Programming Console messages are displayed in English or Japanese.
Page 40: Rs-232C Port Servicing Time (Cpm2A/Cpm2C/Srm1(-V2) Only)
Servicing time (%, valid with bits 08 to 15 are 01) 00 to 99 (BCD, two digits) Default: 5% of cycle time Example: If DM 6616 is set to 0110, the RS-232C port will be serviced for 10% of the cycle time. The servicing time will be 0.34 ms minimum.
Page 41: Minimum Cycle Time
AR area. Example If 0230 is set in DM 6618, an FALS 9F error will not occur until the cycle time exceeds 3 s. If the actual cycle time is 2.59 s, the current cycle time stored in the AR area will be 2590 (ms), but the cycle time read from a Programming Device will be 999.9 ms.
Page 42 DM 6625: IR 009 Time constant for IR 002, IR 004, IR 006, and IR 008 Time constant for IR 001, IR 003, IR 005, IR 007, and IR 009 Default: 0000 (8 ms for each) The nine possible settings for the input time constant are shown below. (Set only the rightmost digit for each setting for IR 000.)
Page 43: Cpm2C Changes In Sw2
CPM2C CPU Units with lot numbers of 0190O (1 Septem- ber 2000) or later. This has resulted in a change to the operation of SW2 on the front of the CPU Unit. Check the lot number to confirm the operation of SW2 for any of the following model numbers before attempting operations.
Page 44 RUN mode Note 1. The default setting for DM 6600, bits 06 to 15 is 00 Hex, i.e., according to the communications switch on the front panel. If SW2 is set for connecting a de- vice other than a Programming Console to the peripheral connector, the CPU Unit will start in RUN mode as soon as power is turned ON.
Page 45 CPM2C Changes in SW2 Section Connections IBM PC/AT or compatible CPM2C-CN111 XW2Z-200S-V XW2Z-500S-V CS1W-CN118...
Page 46: Special Features
SECTION 2 Special Features This section explains special features of the CPM1, CPM1A, CPM2A, CPM2C (including the CPM2C-S), and SRM1(-V2). CPM2A/CPM2C Interrupt Functions .........
Page 47: Cpm2A/Cpm2C Interrupt Functions
STUP(––) is executed to change settings. Note *Input points 00005 and 00006 do not exist in CPM2C CPU Units with only 10 I/O points or in CPM2C-S CPU Units. In these CPU Units, interrupt subroutine num- bers 000 and 001 are allocated to input points 00003 and 00004.
Page 48: Processing The Same Memory Locations With The Main Program
If any of the memory locations being used by the main program are changed in the in- terrupt subroutine, the changes will be lost when data is restored to the previous state when restarting execution of the main program.
Page 49 DM 0000. Although #0010 is moved to DM 0000 in the interrupt program, the addition result that was saved is written to DM 0000 as soon as processing returns to the main program, effec- tively undoing the results of the interrupt program.
Page 50 0010. Therefore, in the comparison at point *1, the contents of DM 0000 and DM 0001 are not equal and processing stops with A in the OFF state. As a result, although the contents of DM 0000 and DM 0010 agree at the value 1234, an in- correct comparison result is reflected in comparison result output A.
Page 51: Interrupt Inputs
Normal (See note.) program (See note.) Interrupt Subroutine program Note Input points 00005 and 00006 do not exist in CPM2C CPU Units with only 10 I/O points or in CPM2C-S CPU Units. Input number Interrupt Subroutine Minimum Interrupt (Note 1)
Page 52 Clock Can be used simultaneously. Note 1. The same input number (from 00003 to 00006) cannot be used for more than one of the following functions: interrupt inputs, interrupt inputs (counter mode), or quick-response inputs. 2. When inputs 00003 to 00006 are set for use as interrupt inputs (counter mode), the input time constants for the relevant inputs are disabled.
Page 53 Interrupt input 3 PC Setup DM 6628 Note Input points 00005 and 00006 do not exist in CPM2C CPU Units with only 10 I/O points or in CPM2C-S CPU Units. Setting the Interrupt With interrupt inputs (interrupt input mode), the subroutine numbers executed Input Number for the input numbers are fixed.
Page 54 Interrupt setting for input 00006* Note *Input points 00005 and 00006 do not exist in CPM2C CPU Units with only 10 I/O points and in CPM2C-S CPU Units. The settings will go into effect when the mode is changed (from PROGRAM to MONITOR/RUN) or when the power supply is turned ON to the CPM2A/ CPM2C.
Page 55 Clearing Interrupt Inputs This function is used to clear input numbers 00003 to 00006 (interrupt inputs 0 to 3). Since interrupt inputs are recorded, masked interrupts will be serviced after the mask is removed unless they are cleared first. Use INT(89) to clear the cause of the interrupt inputs so that they will not be executed when interrupt inputs are permitted (i.e., when the mask is removed).
Page 56 CPM2A/CPM2C Interrupt Functions Section Reading Current Mask Status This function is used to read the current mask status for input numbers 00003 to 00006 (interrupt inputs 0 to 3). (@)INT(89) Interrupt control designation (002: Read current mask status) Fixed at 000.
Page 57 CPM2A/CPM2C Interrupt Functions Section Operation Example Explanation In this example, an interrupt subroutine is executed by turning input 00003 from OFF to ON. The interrupt subroutine adds 1 to DM 0000. Wiring The following diagram shows input wiring in the CPM2A.
Page 58: Interval Timer Interrupts
Executed when input 00003 turns from OFF to ON. 2-1-3 Interval Timer Interrupts One interval timer (precision: 0.1 ms) is supported and it can be set from 0.5 ms to 319,968 ms. There are two interrupt modes: the one-shot mode, in which a single interrupt is executed when the time is up, and the scheduled-interrupt mode, in which interrupts are executed at regular intervals.
Page 59 CPM2A/CPM2C Interrupt Functions Section The following table shows the relationships between interval timer interrupts and the CPM2A/CPM2C’s other functions. Interval timer interrupts Synchronized pulse control Can be used simultaneously. Interrupt inputs Can be used simultaneously. Interval timer interrupts High-speed counters Can be used simultaneously.
Page 60 Start timer In the scheduled-interrupt mode, the timer is reset each time the interrupt pro- gram is called when the set time elapses, and then the interval timer operates again. Be careful with regard to the interrupt program’s execution time and the interval timer’s set time.
Page 61 + 1) x 0.1 ms (0.5 to 319,968 ms) When a constant is set for C2, that value will be taken as the decrementing counter initial value, and the decrementing time interval will become 10 (1 ms). (The SV is specified just as it is, in units of ms.) Reading Timer PVs This function reads interval timer PVs.
Page 62 In this example, the timer is started when the execution condition (00005) turns from OFF to ON. When the time (approx. 1 s) has elapsed, the interrupt subrou- tine is executed one time. When the interrupt subroutine is executed, 1 is added to DM 0000.
Page 63: Precautions On Programming Interrupts
In this example, the timer is started when the execution condition (00005) turns from OFF to ON. Then the interrupt subroutine is executed each time that the set time (approx. 1 s) elapses. Each time the interrupt subroutine is executed, 1 is added to DM 0000.
Page 64 DM 0000 and the result is buffered. The interrupt program writes #0010 to DM 0000, but this is immediately overwritten by the result of the add (1235) as soon as execution of the interrupt program has been completed. In other words, the result of the interrupt program have been consequently nullified.
Page 65 OFF and will remain OFF when execution of the main program is resumed even though the contents of DM 0000 and DM 0010 will be the same as soon as the main program is resumed, i.e., the result of the comparison is not correct...
Page 66: Cpm2A/Cpm2C High-Speed Counters
Interrupt inputs (counter mode) are counters based on inputs to the CPU Unit’s built-in points 00003 to 00006 (00003 to 00004 in CPM2C CPU Units with 10 I/O points and in CPM2C-S CPU Units). These counters have four points, and they can provide either an incrementing or decrementing count depending on the mode setting.
Page 67 CPM2A/CPM2C High-speed Counters Section 2. Input points 00005 and 00006 do not exist in CPM2C CPU Units with 10 I/O points and CPM2C-S CPU Units. High-speed Counter Interrupts Interrupts by High-speed Counter (Count-check Interrupts) Target Value Comparison Interrupts The current count is compared to each target value in the order that they are reg- istered in the table.
Page 68: Using High-Speed Counters
2. When not used for the counter PV storage destination, these words can be used as ordinary IR words. 3. SR 25200 is read once each cycle. Up to one cycle may be required for a reset to occur on the leading edge of phase Z.
Page 69 Clock Can be used simultaneously. Note When inputs 00000 to 00002 are set for use as a high-speed counter, the input time constants for the relevant inputs are disabled. The input time constants re- main in effect, however, for the values for refreshing the relevant input relay area.
Page 70 Select the input mode for the high-speed counter according to the signal type. Differential Phase Input Mode In the differential phase input mode, the count is incremented or decremented according to two differential phase signals with a multiplication of 4 (phase A and phase B). Maximum frequency: 5 kHz...
Page 71 CPM2A/CPM2C High-speed Counters Section Pulse + Direction Input Mode In the pulse + direction input mode, pulse signals and direction signals are input, and the count is incremented or decremented according to the direction signal status. Maximum frequency: 20 kHz...
Page 72 Following the reset, the High-speed Counter Reset Flag (25200) must be turned OFF in order to be able to execute the next reset. To be certain that it is turned OFF, it must be remain OFF for at least one cycle time.
Page 73 The specified subroutine is executed once when the counter PV is greater than or equal to the lower limit and less than or equal to the upper limit in the compari- son table.
Page 74 Interrupt program area Interrupt processing subroutines are defined by SBN(92) and RET(93), just like ordinary subroutines. An SBS UNDEFD error will be generated during the program check while an in- terrupt processing subroutine is being defined, but execution will be normal.
Page 75 CPM2A/CPM2C High-speed Counters Section Wiring Inputs Wire the inputs as shown in the following illustrations, according to the input mode and the reset method. CPM2A Inputs Differential Phase Input Mode Up/Down Pulse Input Mode 00000: CW input 00000: Phase-A input...
Page 76 00000: Pulse input Increment Mode Input terminals Input connector (See above note.) 00002: Reset input 00000: Pulse input 00002: Reset input 00000: Pulse input When phase-Z and reset inputs are not used, 00002 can be used as an ordinary input.
Page 77 04: Use as pulse synchronization control (300 Hz to 20 kHz) The new settings for the System Setup go into effect when operation begins (when PROGRAM mode is changed to MONITOR or RUN mode), or when the CPM2A/CPM2C’s power is turned ON.
Page 78 Register Target Value Comparison Table and Start Comparison These functions register a comparison table to the CPM2A/CPM2C for the pur- pose of count checking in target value comparison. It is also possible to start the comparison along with the registration.
Page 79 Once a comparison table has been registered, it will be saved in the CPM2A/ CPM2C as long as no other comparison table is registered and the mode is not changed to PROGRAM mode (and as long as the power is not turned OFF).
Page 80 Once a comparison table has been registered, it will be saved in the CPM2A/ CPM2C as long as no other comparison table is registered and the mode is not changed to PROGRAM mode (and as long as the power is not turned OFF).
Page 81 SR 249 PV (Leftmost word) Words 248 and 249 are refreshed with every scan, so there may be a discrepan- cy from the exact PV at any given time. When the high-speed counter is not used, words 248 and 249 can be used as work words.
Page 82 1: Overflow/underflow 1: In progress AR 1108 and AR 1109 are refreshed with every scan, so there may be a discrep- ancy from the exact status at any given time. When the status is read by executing PRV(62), AR 1108 and AR 1109 are re- freshed with the same timing.
Page 83 CPM2A/CPM2C High-speed Counters Section AR 1100 through AR 1107 are refreshed with every scan, so there may be a dis- crepancy from the exact PV range comparison result at any given time. When the range comparison result is read by executing PRV(62), AR 1100 through AR 1107 are refreshed with the same timing.
Page 84 Section Wiring (CPM2C) Note The following examples are for Fujitsu-compatible connectors. Input bit ad- dresses and connector pin numbers depend on the models. Refer to the CPM2C Operation Manual (W356) or the CPM2C-S Operation Manual (W377) for de- tails. Input terminals...
Page 85 CPM2A/CPM2C High-speed Counters Section Programming ON for 1 cycle at beginning of operation (71) Register target value comparison table and begin comparison (63) High-speed counter Register target value comparison table and begin comparison Beginning word of comparison table Number of comparisons: 5...
Page 86 In this example, specified interrupt subroutines are executed by matching the high-speed counter’s PV with five range set as a range comparison table. With each interrupt, the data in DM 0000 to DM 0004 is incremented by one. Wiring (CPM2A)
Page 87 Section Wiring (CPM2C) Note The following examples are for Fujitsu-compatible connectors. Input bit ad- dresses and connector pin numbers depend on the models. Refer to the CPM2C Operation Manual (W356) or the CPM2C-S Operation Manual (W377) for de- tails. Input terminals...
Page 88 CPM2A/CPM2C High-speed Counters Section Programming ON for 1 cycle at beginning of operation (71) Register range comparison table and begin comparison (63) High-speed counter Register range comparison table and begin comparison Beginning word of comparison table Lower limit: 9,000 (92)
Page 89: Input Interrupts In Counter Mode
2-2-2 Input Interrupts In Counter Mode The four built-in interrupt inputs in the CPM2A/CPM2C’s CPU Unit can be used in counter mode as inputs of up to 2 kHz. These inputs can be used as either incrementing counters or decrementing counters, triggering an interrupt (i.e., executing an interrupt subroutine) when the count matches the set value.
Page 90 IORF(97) executions. If IORF(97) is executed too frequent- ly, a fatal system error may occur (FALS 9F), stopping operation. The interval between executions of IORF(97) should be at least 1.3 ms + total execution time of the interrupt subroutine.
Page 91 00004 00005* 00006* Note *Input numbers 00005 and 00006 cannot be used for CPM2C CPU Units with 10 I/O points and for CPM2C-S CPU Units. The same input number (from 00003 to 00006) cannot be used for more than one of the following functions: interrupt inputs, interrupt inputs (counter mode),...
Page 92 Incrementing Counter Mode As the set value (SV) is refreshed, the count is incremented from 0, and the inter- rupt subroutine is executed when the present value (PV) matches the SV. The subroutine is executed when the count is up, and the PV is reset to 0.
Page 93 Interrupt setting for input 00006* Note *Input number 00005 and 00006 cannot be used in CPM2C CPU Units with 10 I/O points and in CPM2C-S CPU Units. The setting will go into effect when the mode is changed (from PROGRAM to MONITOR/RUN) or when the power supply is turned ON to the CPM2A/ CPM2C.
Page 94 PV area for input interrupt (counter mode) 3 Refresh Incrementing Counter SV / Refresh Decrementing Counter SV These functions store the counter’s set values in data areas and refresh them by means of INT(89). In this way, they start the count operation for interrupt inputs (counter mode) and they permit interrupts.
Page 95 Note When INT(89) is executed to mask interrupts during counter operation (interrupt control designation 000), counter operation will be stopped and the counter PV will be reset. To use the counter again, start the counter operation again as de- scribed above.
Page 96 SR 247 Interrupt input (counter mode) 3 Words SR 244 to SR 247 are refreshed with every scan, so there may be a dis- crepancy from the exact PV at any given time. Words SR 244 to SR 247 cannot be used as work word even when the interrupt inputs (counter mode) are not used.
Page 97 The following diagram shows input wiring in the CPM2C. Note The following examples are for Fujitsu-compatible connectors. Input bit ad- dresses and connector pin numbers depend on the models. Refer to the CPM2C Operation Manual (W356) or the CPM2C-S Operation Manual (W377) for de- tails.
Page 98: Cpm1/Cpm1A Interrupt Functions
When two interrupts with equal priority are received at the same time, they are executed in the following order: Input interrupt 0 > Input interrupt 1 > Input interrupt 2 > Input interrupt 3 Interval interrupts > High-speed counter interrupts...
Page 99 25503 0000 Note 1. Define interrupt routines at the end of the main program with SBN(92) and RET(93) instructions, just like regular subroutines. 2. When defining an interrupt routine, a “SBS UNDEFD” error will occur during the program check operation, but the program will be executed normally.
Page 100: Input Interrupts
CPM1-20CDR-j 00003 program is program is CPM1A 20CDj j CPM1A-20CDj-j 00004 executed.) CPM1 30CDR j( V1) CPM1-30CDR-j(-V1) 00003 CPM1A 30CDj j CPM1A-30CDj-j 00004 CPM1A-40CDj-j Note If input interrupts are not used, use inputs 00003 to 00006 as regular inputs.
Page 101 Section Input Interrupt Settings Inputs 00003 to 00006 must be set as interrupt inputs in DM 6628 if they are to be used for input interrupts in the CPM1/CPM1A. Set the corresponding digit to 1 if the input is to be used as an interrupt input (input interrupt or counter mode);...
Page 102 If the bit corresponding to an input interrupt turns ON while masked, that input interrupt will be saved in memory and will be executed as soon as the mask is cleared. In order for that input interrupt not to be executed when the mask is cleared, the interrupt must be cleared from memory.
Page 103 Use the following steps to program input interrupts using the Counter Mode. 1, 2, 3... 1. Write the set values for counter operation to the SR words shown in the fol- lowing table. The set values are written between 0000 and FFFF (0 to 65,535).
Page 104: Masking All Interrupts
Do not use INT(89) to mask interrupts unless it is necessary to temporarily mask all interrupts and always use INT(89) instructions in pairs to do so, using the first INT(89) instruction to mask and the second one to unmask interrupts.
Page 105: Interval Timer Interrupts
Scheduled Inter- rupt Mode in which the interrupt is repeated at a fixed interval. The interval timer’s set value can be set anywhere from 0.5 to 319968 ms, in units of 0.1 ms.
Page 106 + 1: Decrementing counter time interval (4 digits BCD; unit: 0.1 ms) : Elapsed time from previous decrement (4 digits BCD; unit: 0.1 ms) The time from when the interval timer is started until the execution of this instruc- tion is calculated as follows:...
Page 107: High-Speed Counter Interrupts
RET(93) 2-3-5 High-speed Counter Interrupts CPM1/CPM1A PCs have a high-speed counter function that can be used in in- crementing mode or up/down mode. The high-speed counter can be combined with input interrupts to perform target value control or zone comparison control that isn’t affected by the PC’s cycle time.
Page 108 Note In incrementing mode, input 00001 can be used as a regular input. When the reset method is used for the software reset, input 00002 can be used as a regular input. Also, even when used for the phase-Z signal and software reset, the input status is reflected inn 00002 of the I/O memory.
Page 109 Phase B Count Count 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 –1 –2 Incremented only Incremented Decremented Note One of the reset methods described below should always be used to reset the counter when restarting it.
Page 110 Note The High-speed Counter Reset Bit (SR 25200) is refreshed once every cycle, so in order for it to be read reliably it must be ON for at least one cycle. The “Z” in “phase-Z” is an abbreviation for “Zero.” It is a signal that shows that the encoder has completed one cycle.
Page 111 Once the count has equaled all of the target values in the table, the target value is set to the first target value in the table, which is again compared to the current counted until the two values are equal.
Page 112 (i.e., during program execution) as long as no other table is saved. Reading the PV There are two ways to read the PV. The first is to read it from SR 248 and SR 249, and the second to use the PRV(62) instruction.
Page 113 There are two ways to change the PV of high-speed counter. The first way is to reset it by using the reset methods. (In this case the PV is reset to 0.) The second way is to use the INI(61) instruction.
Page 114 The corresponding subroutine is executed when the counter’s PV is within the range. Note Always set 8 ranges. If fewer than 8 ranges are needed, set the remaining sub- routine numbers to FFFF. A value of FFFF indicates that no subroutine is to be executed.
Page 115: Srm1(-V2) Interrupt Functions
SRM1(-V2) Interrupt Functions Section The following diagram shows the example ladder program. DM 6642 must be set to 01j0, where j is the reset method which can be set to 0 or 1. 25315 (ON for first cycle) CTBL(63) Registers...
Page 116 + 1: Decrementing time interval (4 digits BCD; unit: 0.1 ms): 0005 to 0320 (0.5 ms to 32 ms) The meanings of the settings are the same as for the one-shot mode, but in the scheduled interrupt mode the timer PV will be reset to the set value and decrementing will begin again after the subroutine has been called.
Page 117 SRM1(-V2) Interrupt Functions Section Stopping the Timer Use the STIM(69) instruction to stop the interval timer. The interval timer will be stopped. (@)STIM(69) : Stop interval timer (010) Application Example In this example, an interrupt is generated 2.4 ms (0.6 ms...
Page 118: Cpm2A/Cpm2C Pulse Output Functions
Note To use pulse outputs, it is necessary to use a CPU Unit with transistor outputs, i.e., either a CPM2A-jjCDT-D or CPM2A-jjCDT1-D.
Page 119: Interval Timer Interrupts
Outputs are possible for only one point at a time with pulse + direction outputs and up/down pulse outputs, so no other pulses can be output.
Page 120 Instruction execution: PULS(65) + SPED(64) (Independent mode) Independent mode Number of set pulses The output is stopped automatically when the set number of pulses has been output. Instruction execution: SPED(64) (Continuous mode) Continuous mode Pulses continue to be output at the set frequency until stopped by the instruction.
Page 121 With ACC(––), the output mode, starting frequency, target frequency, and acceleration/deceleration rate are set, and the pulse outputs are started. From when the pulse outputs are started until they are stopped, they are controlled at a constant-ratio frequency change. Independent Mode Instruction execution: PULS(65) + ACC(––) (Independent mode)
Page 122 PULS(65): For setting the number of output pulses. Create a ladder diagram program. SPED(64): For pulse output control without acceleration and deceleration. INI(61): For stopping pulse outputs and changing the pulse output PV. PRV(62): For reading the pulse output PV and status. Single-phase Pulse Outputs...
Page 123 CPM2A/CPM2C Pulse Output Functions Section Wiring the Outputs Wire the CPM2A outputs as shown in the following illustration. (Pulses can be output independently from pulse outputs 0 and 1. Output 01000: Pulse output 0 (single-phase output) Output 01001: Pulse output 1 (single-phase output) Wire the CPM2C outputs as shown in the following illustration.
Page 124 Note 1. This instruction can be executed only while pulse outputs are stopped. The PV cannot be changed while pulses are being output. If the PV needs to be changed, be sure to stop the pulse output first. 2. This instruction can be used only for changing the frequency and stopping the pulse output.
Page 125 Relative pulses (SV for number of pulses = Number of pulses moved) 001: Absolute pulses (SV for number of pulses = The next PV on the absolute coordinate system, i.e., the pulse output PV + number of pulses moved)* *Absolute pulses can only be specified by PULS(65) when the PV coordinate system in the PC Setup is set for an absolute coordinate system.
Page 126 CPM2A/CPM2C Pulse Output Functions Section cy, and begin pulse outputs. They can also be used to change the frequency if pulse outputs are already in progress. (@)SPED(64) Port specifier (000: Pulse output 0; 010: Pulse output 1) Mode designation (000: Independent; 001: Continuous)
Page 127 Using Data Areas As shown in the following illustration, the pulse output status for pulse output 0 is stored in AR 11, and the pulse output status for pulse output 1 is stored in AR 12. AR 11: Pulse output 0...
Page 128 CPM2A/CPM2C Pulse Output Functions Section Note The flags in AR 11 and AR 12 are refreshed once each cycle, so the values in these words may not reflect the actual status during each cycle, but the flags in AR 11 and AR 12 are refreshed when the status is read with PRV(62).
Page 129 Wire the CPM2A to the motor driver as shown in the following illustration. Motor Driver Wire the CPM2C to the motor driver as shown in the following illustration. In this case, a CPU Unit with sinking transistor outputs is used.
Page 130 In this example, when the execution condition (00005) turns ON, JOG pulses are output at a frequency of 100 Hz from either output 01000 (pulse output 0) or out- put 01001 (pulse output 1). When the execution condition (00005) turns OFF, the output is stopped.
Page 131 CPM2A/CPM2C Pulse Output Functions Section Wire the CPM2C to the motor driver as shown in the following illustration. In this case, a CPU Unit with sinking transistor outputs is used. Note The following examples are for Fujitsu-compatible connectors. Output bit ad- dresses and connector pin numbers depend on the models.
Page 132: Using Pulse Outputs With Variable Duty Ratio
01000 01001 Wiring the Outputs Wire the CPM2A outputs as shown in the following illustration. (Pulses can be output independently from pulse outputs 0 and 1. Output 01000: Pulse output 0 (single-phase output) Output 01001: Pulse output 1 (single-phase output) Wire the CPM2C outputs as shown in the following illustration.
Page 133 (300 Hz to 20 kHz). Synchronized pulse control cannot be used simultaneously. The settings will go into effect when the mode is changed (from PROGRAM to MONITOR/RUN) or when the power supply is turned ON to the PC. Ladder Diagram...
Page 134 These functions set the position for outputting pulses (01000, 01001), the fre- quency, and the duty ratio, and start the pulse outputs. By changing the duty ratio setting and executing PWM(––) again, it is also possible to change the duty ratio while pulse outputs with variable duty ratio are already in progress.
Page 135 Using Data Areas As shown in the following illustration, the pulse output status for pulse output 0 is stored in AR 1115, and the pulse output status for pulse output 1 is stored in AR 1215. AR 11: Pulse output 0...
Page 136 CPM2A/CPM2C Pulse Output Functions Section Note The following examples are for Fujitsu-compatible connectors. I/O bit addresses and connector pin numbers depend on the models. Refer to the CPM2C Opera- tion Manual (W356) or the CPM2C-S Operation Manual (W377) for details. Input connector (See above note.)
Page 137 CPM2A/CPM2C Pulse Output Functions Section Programming (CPM2C Example) Execution condition DIFD (14) 20000 Detects OFF to ON transition in execution condition. Reads the value from the thumb rotary switch. ANDW (34) #000F Value from the thumb rotary switch DM0100 BCD (24)
Page 138: Using Pulse Outputs With Trapezoidal Acceleration And Deceleration
Create a ladder diagram program. ACC(––): For controlling pulse outputs with trapezoidal acceleration and deceleration INI(61): For stopping pulse outputs and changing the pulse output PV. PRV(62): For reading the pulse output PV and status. Pulse Outputs With Trapezoidal Acceleration and Deceleration...
Page 139 CPM2A/CPM2C Pulse Output Functions Section Selecting the Direction Select the pulse output direction control method according to the type of signal Control Method used. Pulse + Direction Outputs Up/down Pulse Outputs Selecting the Pulse Select pulse output 0. Output Number...
Page 140 Note 1. This instruction can be executed only while pulse outputs are stopped. The PV cannot be changed while pulses are being output. If the PV needs to be changed, be sure to stop the pulse output first. 2. This instruction can be used only for changing the frequency and stopping the pulse output.
Page 141 Relative pulses (SV for number of pulses = Number of pulses moved) 001: Absolute pulses (SV for number of pulses = The next PV on the absolute coordinate system, i.e., the pulse output PV + number of pulses moved)* *Absolute pulses can only be specified by PULS(65) when the PV coordinate system...
Page 142 These functions set the output mode, the target frequency, the starting frequen- cy, and the acceleration/deceleration rate, and they begin pulse outputs. They can also be used to change the frequency, by accelerating or decelerating at the specified acceleration/deceleration rate, if pulse outputs are already in progress in continuous mode.
Page 143 Change PV data (Rightmost, leftmost digits) Register the PV data to be changed. Leftmost 4 digits 96,777,215 to 16,777,215 Negative numbers are expressed by turning ON the leftmost bit. Note The pulse output PV can be changed only while the pulse output is stopped.
Page 144 Word 229 PV (Leftmost) SR 228 and SR 229 are refreshed once each cycle, so the values in these words may not reflect the actual status during each cycle. SR 228 and SR 229 are re- freshed immediately when their status is read with PRV(62).
Page 145 CPM2A/CPM2C Pulse Output Functions Section SR 228 to SR 231 cannot be used as work words even when pulse outputs are not being used. When the PV is read by executing PRV(62), SR 228 to SR 231 are refreshed with the same timing.
Page 146 PULS(65) execution ACC(––) execution Output 0 in progress Output 1 in progress Output completion Output status Set number of pulses Continuous Mode with Acceleration and Deceleration 1 Frequency Time ACC(––) execution (1) ACC(––) execution (2) INI(61) execution Output 0 in progress...
Page 147 Set number of pulses Application Example Positioning Explanation In this example, when the execution condition (00005) turns ON, 1000 pulses are output from output 01000 (pulse output 0) in a trapezoidal acceleration/de- celeration pattern as shown in the following diagram. Frequency (Hz)
Page 148 Wire the CPM2A to the motor driver as shown in the following illustration. Motor Driver Wire the CPM2C to the motor driver as shown in the following illustration. In this case, a CPU Unit with sinking transistor outputs is used.
Page 149 Explanation In this example, when the execution condition (00005) turns ON, JOG pulses are output at a frequency of 100 Hz from either output 01000 (CW direction) or out- put 01001 (CCW direction). When the execution condition (00005) turns OFF, the output is stopped.
Page 150 CPM2A/CPM2C Pulse Output Functions Section Wire the CPM2C to the motor driver as shown in the following illustration. In this case, a CPU Unit with sinking transistor outputs is used. Note The following examples are for Fujitsu-compatible connectors. Output bit ad- dresses and connector pin numbers depend on the models.
Page 151 CPM2A/CPM2C Pulse Output Functions Section Programming 00005 (Execution condition) (13) Detects turning ON of execution condition. (14) Detects turning OFF of execution condition. (Direction designator) AR1115 Output in CW direction ACC(––) Pulse output 0 Continuous mode, up/down pulses, CW direction...
Page 152: Cpm1A Pulse Output Functions
The CPM1A PCs with transistor outputs have a pulse output function capable of outputting a pulse of 20 Hz to 2 kHz (single-phase). Either IR 01000 or IR 01001 can be selected for pulse output, and the pulse output can be set to either the...
Page 153: Programming Example In Continuous Mode
In N, set the beginning word address of the words where the number of pulses is set. Store the number of pulses in words N and N+1, in eight digits BCD, with the leftmost four digits in N+1 and the rightmost four digits in N.
Page 154: Changing The Frequency
1. Use SPED(64) to set the frequency to 0. 2. Use INI(61) to stop the pulse output. Using SPED(64) The first method is to use SPED(64) to stop the pulse output by setting the fre- quency to 0. For details, refer to 2-6-4 Changing the Frequency. Using INI(61)
Page 155: Synchronized Pulse Control (Cpm2A/Cpm2C Only)
Note A CPU Unit with transistor outputs is required in order to use synchronized pulse control, i.e., either a CPM2A-jjCDT-D or CPM2A-jjCDT1-D.
Page 156 Synchronized Pulse Control (CPM2A/CPM2C Only) Section The directions of pulse inputs are all ignored. The frequency of a pulse that has been input is read, without regard to the direction. The following table shows the relationships between synchronized pulse control and the CPM2A’s other functions.
Page 157 Select the input mode. mode, up/down pulse input mode, increment mode Select the pulse synchronization Input frequency: 10 Hz to 500 Hz; 20 Hz to 1 kHz; 300 Hz to 20 kHz input frequency. Input numbers: 00000, 00001, and 0002 Wire the inputs and outputs.
Page 158 Selecting the Pulse Select one of the following as the input frequency range: 10 Hz to 500 Hz, 20 Hz Synchronization Input to 1 kHz, or 300 Hz to 20 kHz. For more information on input frequencies, refer to Frequency the following diagrams.
Page 159 Synchronized Pulse Control (CPM2A/CPM2C Only) Section Increment Mode In the increment mode, pulse signals are input and the count is incremented with each pulse. Phase-B inputs can be used as ordinary inputs. Pulse inputs 1,000 Frequency = Wiring the Inputs Input Wiring Wire the CPM2A inputs as shown in the following diagram.
Page 160 Wire the CPM2C inputs as shown in the following diagram. Note The following examples are for Fujitsu-compatible connectors. Input bit ad- dresses and connector pin numbers depend on the models. Refer to the CPM2C Operation Manual (W356) or the CPM2C-S Operation Manual (W377) for de- tails.
Page 161 Wire the CPM2C outputs as shown in the following diagram. (See above note.) Output connector 01000: Pulse output 0 01001: Pulse output 1 PC Setup The settings in the PC Setup related to synchronized pulse control are listed in the following table. Word Bits Function Setting...
Page 162 Port specifier (000: High-speed counter) Control designation (005: Stop synchronized control) Fixed: 000 Note The pulse output can also be stopped by switching the PC to PROGRAM mode. Read Input Frequency This function reads the input frequency PV. Using an Instruction...
Page 163 0: Stopped 1: Output in progress AR 1115 and AR 1215 are refreshed once each cycle, so there may be a discrep- ancy from the exact PV at any given time. When the PV is read by executing PRV(62), AR 1112 and AR 1212 are refreshed...
Page 164 Wiring Wire the CPM2A as shown in the following illustration. Orange White Black Blue Rotary encoder Brown Motor driver Wire the CPM2C as shown in the following illustration. In this case, a CPU Unit with sinking transistor outputs is used.
Page 165 Brown Orange 24 VDC White Black Note For details regarding motor driver wiring to outputs and rotary encoder wiring to inputs, refer to the CPM2A Operation Manual (W352)/CPM2C (W356) Opera- tion Manual CPM2C-S Operation Manual (W377). PC Setup DM 6642 0: Differential phase input 02: Use as pulse synchronization output.
Page 166 Synchronized Pulse Control (CPM2A/CPM2C Only) Section Programming (Example for CPM2C) Execution condition 00005 DIFD (14) 20000 Detects OFF to ON transition in execution condition. SYNC Executes synchronized pulse control. High-speed counter Pulse output 0 First word containing frequency factor DM0000 20000 Stops synchronized pulse control.
Page 167: Data Computation Standards
Delay Pulse input Pulse output Maximum delay (ms) = Setting in DM 6642 (see below) + One period of the current pulse output B 2 + 10 Setting of Frequency range Delay DM 6642 bits 08 to 15...
Page 168: Analog I/O Functions (Cpm1/Cpm1A/Cpm2A/Cpm2C Only)
990 to 1010 Hz. The multiplication factor of 300%, however, would make this 2970 to 3030 Hz. There would also be an error of 1% in the frequency of the output pulse, so the output would be in the range 2940 to 3060 Hz.
Page 169: Compobus/S I/O Master Functions (Srm1(-V2) And Cpm2C-S Only)
Slave Interrupts Input bits in IR 000 to IR 007 and output bits in IR 010 to IR 017 are used as inter- rupts for CompoBus/S I/O Terminals. The CompoBus/S I/O Terminal interrupts (IN 0 to 15 and OUT 0 to 15) are allocated as indicated in the following table.
Page 170 3. The Slave Add Flag turns ON when a slave joins the communications. When the power to the CPU Unit is turned OFF and ON again all bits will turn OFF. 4. The Slave Communications Error Flag turns ON when a slave participating in the network is separated from the network.
Page 171: Analog Controls (Cpm1/Cpm1A/Cpm2A Only)
CPU Unit’s adjustment switches to words in the CPU Unit’s I/O me- mory. This function is very useful when there are set values that need to be pre- cisely adjusted during operation. These set values can be changed just by turn- ing the adjustment switches on the CPU Unit.
Page 172 CPM1A/CPM2A The analog setting for control 0 is in SR 250. The analog setting for control 1 is in SR 251. Note The above diagram shows the CPM2A, but the settings are the same for the CPM1A. Caution The analog setting may change with changing temperatures. Do not use the...
Page 173 Analog control 1 SV storage area In the following example program, the analog control SV (0000 to 0200 BCD) stored in SR 250 is set as a timer SV. The timer’s set range is 0.0 s to 20.0 s. Start bit...
Page 174: Quick-Response Inputs
Quick-response Operation Quick-response inputs have an internal buffer, so input signals shorter than one cycle can be detected. Signals with a pulse width as short as 0.2 ms can be de- tected, regardless of their timing during the PC cycle.
Page 175: Cpm2A/Cpm2C Quick-Response Inputs
If they are not used for any of these purposes, then they can be used as ordinary inputs. 2. Input number 00006 does not exist in CPM2C CPU Units with 10 I/O points. The following table shows the relationships between quick-response inputs and the CPM2A/CPM2C’s other functions.
Page 176 Quick-response input 3 PC Setup DM 6628 Wiring the Inputs Wire the CPM2A’s inputs as shown in the following diagram. Input 00003: Quick-response input 0 Input 00004: Quick-response input 1 Input 00005: Quick-response input 2 Input 00006: Quick-response input 3...
Page 177 Wire the CPM2C’s inputs as shown in the following diagram. Note The following examples are for Fujitsu-compatible connectors. Input bit ad- dresses and connector pin numbers depend on the models. Refer to the CPM2C Operation Manual (W356) or the CPM2C-S Operation Manual (W377) for de- tails.
Page 178: Macro Function
(step 3 above). Note SR 232 through SR 239 can be used as work bits when MCRO(99) is not used. The first input word and the first output word can be specified not with I/O bits, but also with other bits (such as HR bits, work bits, etc.) or with DM words.
Page 179: Calculating With Signed Binary Data
Calculating with Signed Binary Data Section 2-16 Application Example When a macro is used, the program can be simplified as shown below. Macro not used Macro used 25313 (Always ON) 00000 20001 MCRO(99) 20000 20000 00001 00002 MCRO(99) 20001 00200...
Page 180: Differential Monitor
2-16-1 Definition of Signed Binary Data Signed binary data is manipulated using 2’s complements and bit 15 is used as the sign bit. The range of data that can be expressed using one word is as fol- lows:–32,768 to 32,767 (8000 to 7FFF hexadecimal).
Page 181: Expansion Instructions (Cpm2A/Cpm2C/Srm1(-V2) Only)
CPM2C-S), and SRM1(-V2) to aid in special programming needs. Function codes can be assigned to up to 18 of the expansion instructions to enable using them in programs. This allows the user to pick the instructions needed by each CPM2A, CPM2C, or SRM1(-V2) program to more effectively use the function codes required to input instructions.
Page 182: Cpm2A/Cpm2C/Cpm2C-S Expansion Instructions
The following 18 function codes can be used for expansion instructions: 17, 18, 19, 47, 48, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 87, 88, and 89. The function code assignments can be changed with a Programming Console or the Support Software.
Page 183: Srm1(-V2) Expansion Instructions
The following 18 function codes can be used for expansion instructions: 17, 18, 19, 47, 48, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 87, 88, and 89. The function code assignments can be changed with a Programming Console or the Support Software.
Page 184: Using The Cpm2A/Cpm2C Clock Function
AR 2100 through AR 2107 (day of week). 3. Turn ON AR 2115 (Clock Set Bit) when the time set in step 2 is reached. The clock will start operating from the time that is set, and the Clock Stop Bit and Clock Set BIt will be turned OFF automatically.
Page 185: Using Expansion Units
CPM1A-TS001/002/101/102 and CPM2C-TS001/101 Temperature Sensor Units; the CPM1A-SRT21 and CPM2C-SRT21 CompoBus/S I/O Link Units; and the CPM1A-DRT21 DeviceNet I/O Link Unit. The CPM1A-MAD11 and CPM2C-MAD11 Analog I/O Units provide the same functions, and are thus described in the same section even though they are supported by different PCs.
Page 186: Analog I/O Units
With the maximum of 3 Analog I/O Units connected, 6 analog inputs and 3 ana- log outputs are possible. The analog input range can be set to 0 to 10 VDC, 1 to 5 VDC, or 4 to 20 mA with a resolution of 1/256.
Page 187 1. With analog outputs it is possible to use both voltage outputs and current outputs at the same time. In this case however, the total output current must not exceed 21 mA. 2. The conversion time is the total time for 2 analog inputs and 1 analog output. Part Names Expansion connector...
Page 188 Analog I/O Units Section Analog I/O Signal Ranges Analog Input Signal Ranges 0 to 10 V inputs 1 to 5 V inputs 4 to 20 mA inputs Conversion value Conversion value Conversion value Input signal Input signal Input signal Analog Output Signal Ranges –10 to +10 V outputs...
Page 189 Analog I/O Units Section Using Analog I/O Analog inputs: 0 to 10 V, 1 to 5 V, or 4 to 20 mA Set the I/O range Analog outputs: 0 to 10 V, –10 to +10 V, or 4 to 20 mA Connect the Unit Connect the Analog I/O Unit.
Page 190 Recorder Other Note Word (n + 1) can be used for either the range code or the analog output set value. Setting I/O Signal Range The I/O signal range is set by wiring the I/O terminal and by writing the range code to the Analog I/O Unit’s output word.
Page 191 1 to 5 V or 4 to 20 mA –10 to 10 V or 4 to 20 mA Write the range code to the Analog I/O Unit’s output word (n + 1) in the first cycle of program execution. SR 25315 First Cycle Flag...
Page 192 (m + 1) (m + 2) 2 analog inputs 1 analog output (n + 1) For example, in the following diagram an Analog I/O Unit is connected to a CPU Unit with 30 I/O points. IR 002 IR 000 Input address...
Page 193 Note The Open-circuit Detection Flag is turned ON when the input signal range is set to 1 to 5 V or 4 to 20 mA and the input signal falls below 1 V or 4 mA. (Open cir- cuits are not detected when the input signal range is set to 0 to 10 V.)
Page 194 Note Analog input data will be 0000 until initial processing has been completed. Ana- log output data will be 0 V or 0 mA until the range code has been written. After the range code has been written, the analog output data will be 0 V or 4 mA if the range is 0 to 10 V, –10 to 10 V, or 4 to 20 mA.
Page 195 Analog Input Program Example Analog I/O Unit Connection In this example, an Analog I/O Unit is connected to a CPU Unit with 30 I/O points. I/O words are allocated to the Analog I/O Unit beginning with the next word ad- dress following the last words allocated to the CPU Unit.
Page 196 Reads analog input 1’s converted value. Execution TIM000 condition MOV (21) Reads analog input 2’s converted value. DM0001 Execution TIM000 condition MOV (21) DM0010 The content of DM0010 is written to the output word as the analog output set value.
Page 197: Cpm1A-Mad11 And Cpm2C-Mad11 Analog I/O Units
Unit The analog input range can be set to 0 to 5 VDC, 1 to 5 VDC, 0 to 10 VDC, –10 to 10 VDC, 0 to 20 mA, or 4 to 20 mA. The inputs have a resolution of 1/6000.
Page 198 Analog I/O terminals Analog I/O Terminals Connected to analog I/O devices. Expansion I/O Connected to the CPU Unit or previous Expansion Unit. The cable is provided Connecting Cable with the Unit and cannot be removed. Caution Do not touch the cables during operation. Static electricity may cause operating errors.
Page 199 Connected to the expansion I/O input connector on the next Expansion (I/O) Connector Unit. Note 1. A maximum of 5 Expansion (I/O) Units can be connected to the CPU Unit and the total number of allocated words must be 10 maximum for inputs and 10 maximum for outputs.
Page 200 –10 to 10 V The –10- to 10-V range corresponds to the hexadecimal values F448 to 0BB8 (–3000 to 3000). The entire data range is F31C to 0CE4 (–3300 to 3300). A neg- ative voltage is expressed as a two’s complement.
Page 201 6000). The entire data range is FED4 to 189C (–300 to 6300). Inputs between 0.8 and 1 V are expressed as two’s complements. If the input falls below 0.8 V, open-circuit detection will activate and converted data will be 8000.
Page 202 0 to 10 V The hexadecimal values 0000 to 1770 (0 to 6000) correspond to an analog volt- age range of 0 to 10 V. The entire output range is –0.5 to 10.5 V. Specify a nega- tive voltage as a two’s complement.
Page 203 The open-circuit detection function is activated when the input range is set to 1 to Function for Analog 5 V and the voltage drops below 0.8 V, or when the input range is set to 4 to Inputs 20 mA and the current drops below 3.2 mA. When the open-circuit detection...
Page 204 Using Analog I/O Connect the Analog I/O Unit. Connect the Unit. Analog inputs: 0 to 5 VDC, 1 to 5 VDC, 0 to 10 VDC, –10 to 10 VDC, 0 to 20 mA, or 4 to 20 mA Set the I/O ranges.
Page 205 Expansion I/O Unit. Recorder Other Note Word (n + 1) can be used for either the range code or the analog output set value. Connecting the This section describes how to connect an Analog I/O Unit to the CPU Unit.
Page 206 I/O Unit I/O Allocation I/O is allocated for the Analog I/O Unit in the same way as other Expansion Units or Expansion I/O Units starting from the next word following the last allocated word on the CPU Unit or previous Expansion Unit or Expansion I/O Unit. When “m”...
Page 207 After the range code has been set, 0 V or 0 mA will be output for the 0 to 10-V, –10 to 10-V, or 0 to 20-mA ranges, and 1 V or 4 mA will be output for the 1 to 5-V and 4 to 20-mA ranges until a convertible value has been written to the output word.
Page 208 Analog I/O Units Section Once the range code has been set, it is not possible to change the setting while power is being supplied to the CPU Unit. To change the I/O range, turn the CPU Unit OFF then ON again.
Page 209 2. When an input is not being used, short the + and – terminals. 3. Separate wiring from power lines (AC power supply lines, high-voltage lines, etc.) 4. When there is noise in the power supply line, install a noise filter on the input section and the Power Supply Unit. CPM2C-MAD11 Internal Circuits...
Page 210 24 VDC For example, if analog input device 2 is outputting 5 V and the same power sup- ply is being used as shown above, about 1/3, or 1.6 V, will be applied at the input for input device 1.
Page 211 0 V or 0 mA if the range is 0 to 10 V, –10 to 10 V, or 0 to 20 mA, or it will be 1 V or 4 mA if the range is 1 to 5 V or 4 to 20 mA.
Page 212 #8000 25506(=) 01000 Open-circuit alarm Execution TIM005 condition MOV (21) Reads analog input 1’s converted value. DM0001 Execution TIM005 condition MOV (21) DM0010 The content of DM 0010 is written to the output word as the analog output set value.
Page 213: Temperature Sensor Units
3-2-1 CPM1A/CPM2A Temperature Sensor Units With the CPM1A or CPM2A, up to three Expansion Units or Expansion I/O Units can be connected to the CPU Unit. One, two, or three of these Units can be CPM1A-TS001 or CPM1A-TS101 Temperature Sensor Units. If a CPM1A-...
Page 214: Cpm2C Temperature Sensor Units
Temperature Sensor Units Section 2. Accuracy for a K-type sensor at –100 C or less is 4_C 1 digit max. 3-2-2 CPM2C Temperature Sensor Units With the CPM2C (including the CPM2C-S), up to four CPM2C-TS001/TS101 Temperature Sensor Units can be connected (up to three Units for the CPM2C-S).
Page 215: Using Temperature Sensor Units
Words are allocated to Temperature Sensor Units just like other Expansion I/O Units and Expansion Units: In the order in which the Units are connected. A Tem- perature Sensor Unit will thus be allocated the next input words after the Unit to which it is connected (CPU Unit or other Unit).
Page 216 IR 013 Output word addresses IR 011 None IR 012 CPM2C Temperature Sensor Unit Allocations Up to four CPM2C-TS001/101 Temperature Sensor Units can be connected. Up to a total of five Expansion I/O Units and Expansion Units can be connected (in-...
Page 217 Temperature Sensor Units.) Up to three Units can be connected to the CPM2C-S. No matter how many Units are connected, however, no more than 0 input words and 10 output words can be allocated in one PC. There are no restrictions on the order in which Units can be connected.
Page 218 Rotary Switch Used to set the temperature input range. DIP Switch Settings The DIP switch is used to set the temperature unit ( C or F) and the number of decimal places used. CPM1A-TSjjj CPM2C-TSjjj 0.01 1 or 0.1...
Page 219 Section Note 1. Turn OFF the power supply before changing the temperature range setting. 2. Do not touch the DIP switch or rotary switches while power is turned ON. Static electricity may cause malfunctions. Rotary Switch Setting The rotary switch is used to set the temperature range.
Page 220 CPM1A/CPM2A Temperature Sensor Units Thermocouples CPM1A-TS001 Either K or J thermocouples can be connected, but both of the thermocouples must be of the same type and the same input range must be used for each. Input 0 Input 1 Input 0 Input 1 –...
Page 221 Platinum Resistance Thermometers CPM1A-TS101 Either Pt100 or JPt100 platinum resistance thermometers can be connected, but both of the thermometers must be of the same type and the same input range must be used for each. Input 1 Input 1 Input 0...
Page 222: Ladder Programming
CPM2C Temperature Sensor Units CPM2C-TS001 (Thermocouples) Either K or J thermocouples can be connected, but both of the thermocouples must be of the same type and the same input range must be used for each. 0– Temperature input 0 1–...
Page 223 Note Input data will be 7FFE until actual conversion starts. Handling Unit Errors If an error occurs in an Expansion Unit, the Error Flags in AR 0200 to AR 0204 will be turned ON ( AR 0200 to AR 0202 for the CPM1A/CPM2A). Refer to page 572 for details.
Page 224 IR 000 Temperature unit setting: OFF ( C) IR 002 Two-decimal-place Mode: OFF (normal) Input range setting: 1 (K2, 0.0 to 500.0 C) Temperature input 0 storage word: IR 001 Temperature input 1 storage word: IR 002 Outputs Outputs IR 010...
Page 225 25506(=) ON when an open-circuit alarm or Unit error has been 01000 detected for input 0. CMP (20) Checks to see if the temperature data in IR 001 has exceeded 500.0 C (1388 Hex without decimal point). #1388 25505(>) 01001 ON for an input 0 temperature error 25507(<)
Page 226 The following programming example shows how to convert the data for temper- ature input 0 to BCD and store the result in DM 0000 and DM 0001. “0001” is stored in DM 0001 when the input data is a negative value. The following system configuration is used.
Page 227 #0001 DM0001 Operation Binary to BCD conversion IR 001 DM 0000 CY (when using SCL2 instruction) DM 0001 1: Negative, 0: Non-negative 0: If data non-negative, “0000” stored in DM 0001 1: If data negative, “0001” stored in DM 0001...
Page 228: Two-Decimal-Place Mode
Section 3-2-8 Two-decimal-place Mode If pin 2 on the DIP switch is turned ON, values are stored to two decimal places. In this case, temperature data is stored as 6-digit signed hexadecimal (binary) data with 4 digits in the integer portion and 2 digits after the decimal point. The actual data stored in memory is 100 times the actual value, i.e., the decimal point...
Page 229 Temperature Sensor Units Section Data Conversion Some examples of the data stored for various temperature inputs are provided Examples below. Example 1 Temperature: 1,130.25 C 100: 113025 Temperature Data: 01B981 (hexadecimal for 113025) Leftmost 3 Digits and Flags Flags Bits...
Page 230 2. Be sure that the data is read at least once every 125 ms to allow for the CPU Unit’s cycle time and communications time. Correct data may not be ob-...
Page 231 Outputs Outputs Outputs IR 010 IR 011 None In this example, 100 times the temperature data for temperature input 0 is stored in binary form in DM 0100 to DM 0102. IR 200 Leftmost data IR 002 Temperature input 0...
Page 232 Temperature Sensor Units Section 25315 (First Scan Flag) MOV (21) Sets DM 0103 and DM 0102 to #0000 #0100 and #0000, respectively. DM0102 MOV (21) #0100 25313 DM0103 (Always ON Flag) CMP (20) Detects completion of input 0 initialization. #7FFE 25506(=) ON when input 0 has been initialized.
Page 233 IR 202 IR 201 HR 01 HR 00 The 2’s complement data in IR 202 and IR 201 is subtracted, as binary data, from the data in DM 0103 and DM 0102 and placed in HR 01 and HR 00.
Page 234: Compobus/S I/O Link Units
CompoBus/S CPU Unit I/O Link Unit Special Flat Cable, 2-core VCTF cable, or 4-core VCTF cable (You cannot mix Special Flat Cable, 2-core VCTF cable, and 4-core VCTF cable. Use only one type of cable.) Cable Model Specifications Special Flat Cable SCA1-4F10 4-core flat cable, 0.75 mm...
Page 235 I/O words are allocated to the CompoBus/S I/O Link Unit in the same way as Expansion I/O Units or other Expansion Units, the next available input and out- put words are allocated. When “m” is the last allocated input word and “n” is the...
Page 236 The 8 bits of I/O data are not always transmitted simultaneously. In other words, 8 bits of data transmitted from the Master CPU Unit at the same time will not al- ways reach the Slave CPU Unit simultaneously, and 8 bits of data transmitted from the Slave CPU Unit at the same time will not always reach the Master CPU Unit simultaneously.
Page 237 CompoBus/S I/O Link Units Section DIP Switch Settings Use the DIP switch to set the CompoBus/S I/O Link Unit’s node number, commu- nications mode, and the status of output data when a communications error oc- curs. CPM1A-SRT21 DIP switch CPM2C-SRT21...
Page 238 CompoBus/S I/O Link Units Section 3. The long-distance communications mode can be used only when one of the following Master Units is connected: C200HW-SRM21-V1, CQM1-SRM21-V1, or SRM1-C0j-V2. Wiring the CompoBus/S Wire the CompoBus/S communications path as shown in the following dia- Communications Path grams.
Page 239: Devicenet I/O Link Unit
DeviceNet I/O Link Unit CPU Unit From the standpoint of the CPU Unit, the 32 input bits and 32 output bits allo- cated to the DeviceNet I/O Link Unit are identical to input and output bits allo- cated to Expansion I/O Units even though the DeviceNet I/O Link Unit does not control external inputs and outputs.
Page 240 Power not supplied. Handling Unit Errors If an error occurs in the DeviceNet I/O Link Unit, the Error Flags in AR 0200 to AR 0202 will be turned ON. The addresses of the Error Flags are in the order that the Expansion Units are connected in the PC, with AR 0200 used for the Expan- sion Unit closest to the CPU Unit.
Page 241 DeviceNet I/O Link Unit Section Connecting the Connect the DeviceNet I/O Link Unit to the CPU Unit. Up to three Units can be DeviceNet I/O Link Unit connected to the CPM1A/CPM2A. When Expansion I/O Units or other Expan- sion Units are also connected, they can be connected in any order from the CPU Unit.
Page 242 1. Set the rotary switches before turning ON the power supply. The switch set- tings are read only at startup. 2. Any node address from 0 through 63 can be set as long as it hasn’t been set on another slave node.
Page 243 Section Hold/Clear Remote Outputs When the DeviceNet Unit is used as a slave, pin 4 is used to set whether to hold or clear remote outputs when a communications error occurs. Note When using AR 02 (Expansion Unit Error Flags) in the program, turn ON pin 4 on the DIP switch.
Page 244 Refer to the DeviceNet Slaves Operation Manual (W347) for details on the re- sponse time. The data read/write time for one cycle for the CPM1A-DRT21 is approximately 0.5 ms. Add a maximum of 1 ms to the I/O response time.
Page 245: Communications Functions
SECTION 4 Communications Functions This section describes how to use the communications functions provided in the CPM1, CPM1A, CPM2A, CPM2C (includ- ing the CPM2C-S), and SRM1(-V2) PCs. Introduction .............
Page 246: Introduction
Host Link Communications The CPM1/CPM1A PCs are compatible with the Host Link System, which allows up to 32 PCs to be controlled from a host computer. An RS-232C Adapter is used for 1:1 communications and an RS-422 Adapter and B500-AL004 Link Adapter are used for 1:N communications.
Page 247: Cpm1/Cpm1A Communications Functions
OK) 12 to 15 Communications mode 0: Host Link; 2: 1:1 PC Link Slave; 3: 1:1 PC Link Master; 4: 1:1 NT Link DM 6651 00 to 07 Baud rate 00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K...
Page 248: One-To-One Nt Link Communications
CPM1/CPM1A Communications Functions Section 3. If an out-of-range value is set, the following communications conditions will result. In that case, reset the value so that it is within the permissible range. Communications mode: Host Link Communications format: Standard settings (1 start bit, 7-bit data; 2 stop bits, even parity,...
Page 249: One-To-One Pc Link Communications
CPM2C, CQM1, C200HX/HG/HE, or C200HS PC through an RS-232C Adapter and standard RS-232C cable. One of the PCs will serve as the Master and the other as the Slave. The 1:1 PC Link can connect up to 256 bits (LR 0000 to LR 1515) in the two PCs.
Page 250 LR15 Limitations of 1:1 PC Links Only the 16 LR words from LR 00 to LR 15 can be linked in the CPM1/CPM1A, so with a CPM1/CPM1A use only those 16 words in the CQM1 or C200HS when making a 1:1 PC Link with one of those PCs.
Page 251: Cpm2A/Cpm2C Communications Functions
PC sends responses to commands issued from a host computer and can be used to read or write data in the PC’s data areas and control some PC operations. There is no need for a communications program in the PC. Host Link communications can be used through the peripheral port or the CPM2A/ CPM2C’s RS-232C port.
Page 252 CPM2A/CPM2C Communications Functions Section CPM2A One-to-one Communications OMRON Programmable Terminal CPM2A RS-232C port connection CPM2A RS-232C port connection (See note.) (See note.) Note When connecting to the peripheral port, an RS-232C Adapter or computer connection cable (CQM1-CIF01 or CQM1-CIF02) is necessary.
Page 253 CPM2C-CIF11 CPM2C CPU Unit CPM2C-CIF21 Note The CSW1-CN226/626 can be connected directly to the CPU Unit. With the CPM2C-CIF01-V1, the cable switch (SW1) can be turned ON to enable connect- ing to a personal computer with a CS1W-CN226/CN626 Connecting Cable.
Page 254 CPM2A/CPM2C Communications Functions Section CPM2A 1:N Communications B500-AL004 IBM PC/AT Link Adapter or compatible CPM2A RS-232C CPM2A peripheral port connection port connection NT-AL001 RS-232C/RS-422 CPM1-CIF01 RS-422 Adapter Conversion Adapter...
Page 255 IBM PC/AT or Connecting Cable compatible computer XW2Z-200S-V (2 m) XW2Z-500S-V (5 m) B500-AL004 or NT-AL001 (requires +5 V) (See notes 1 and 2.) RS-422 (Total length: 500 m max.) When using the port as a peripheral port CPM2C CPM2C...
Page 256 The block of data transferred in a single transmission is called a “frame.” A single frame is configured of a maximum of 131 characters of data. The right to send a frame is called the “transmission right.” The Unit that has the transmis- sion right is the one that can send a frame at any given time.
Page 257 Long Transmissions The largest block of data that can be transmitted as a single frame is 131 charac- ters. A command or response of 132 characters or more must therefore be di- vided into more than one frame before transmission. When a transmission is split, the ends of the first and intermediate frames are marked by a delimiter instead of a terminator.
Page 258 Frame (response) Dividing Responses As each frame is received by the host computer, a delimiter is transmitted to the CPM2A/CPM2C. After the delimiter has been transmitted, the CPM2A/CPM2C will transmit the next frame. This procedure is repeated until the entire response has been transmitted.
Page 259 Transmissions erations, be careful not to divide into separate frames data that is to be written into a single word. As shown in the illustration below, be sure to divide frames so that they coincide with the divisions between words.
Page 260 ..520 IF FCSD$ < > FCSP$ THEN FCSCK$ = ” ERR ” 530 PRINT ” FCSD$ = ” ; FCSD$ , ” FCSP$ = ” ; FCSP$ , ” FCSCK$ = ” ; FCSCK$ 540 RETURN ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––...
Page 261 Not Valid Valid PROGRAM WRITE Valid Valid Valid COMPOUND COMMAND Valid Valid Valid ABORT (command only) Valid Valid Valid INITIALIZE (command only) Valid Valid Not Valid TXD RESPONSE (response only) Undefined command (response only) Note ---: Not affected by the mode.
Page 262 Check the relation between the Not executable in RUN mode The command that was sent can- command and the PC mode. not be executed when the PC is in RUN mode. Not executable in MONITOR mode The command that was sent can- not be executed when the PC is in MONITOR mode.
Page 263 RS-232C port are governed by the standard Host Link settings (1 start bit, 7 data bits, 2 stop bits, even parity, and 9,600 bps baud rate). Note When a Programming Console is connected to the peripheral port, communica- tions with the Programming Console are unaffected by either the communica- tions switch or PC Setup.
Page 264 When SW 2 is set to ON, the status of SW 1 determines whether communica- tions through the peripheral port and RS-232C port are governed by the settings in the PC Setup or the standard settings (1 start bit, 7 data bits, 2 stop bits, even parity, and 9,600 bps baud rate).
Page 265 Set the DIP switch on the NT-AL001 RS-232C/RS-422 Conversion Adapter. Normally ON ON when the Unit is at the end of the transmission path. OFF in all other cases. Used as a 4-conductor method. (Both switches set to OFF) According to RS-232C CTS control (5: OFF, 6: ON)
Page 266 RS-232C port is used. Settings for RS-232C Port Note If SW1 on the front panel of the CPU Unit is ON, the RS-232C port will operate with the default settings regardless of the settings in DM 6645 to DM 6649.
Page 267 AR 1302 will turn ON.) Note 1. If SW1 on the front panel of the CPU Unit is ON, the peripheral port will oper- ate with the default settings regardless of the settings in DM 6645 to DM 6649.
Page 268 AR 1302 will turn ON.) DM 6654 00 to 07 Start code (Peripheral port, effective when bits 08 to 11 of DM 6653 are set to 1.) 01 to FF (Hex) 08 to 15 No. of bytes of data received (Peripheral port, effective when bits 12 to 15 of DM 6653 are set to 0.)
Page 269 ASC( MID$ ( SEND$ , IFCS , 1 ) ) 1150 NEXT 1160 FCS$ = RIGHT$ ( ”0” + HEX$ ( FCS ) , 2 ) 1170 ’ –––Communications execute––––––––––––––––––––––––––––––––––––––––––––––– 1180 ZZZ$ = SEND$ + SCS$ + ”*” + CHR$(13) 1190 PRINT #1 , ZZZ$ ;...
Page 270 0: RS-232 port; 1: Peripheral port When Host Link communications are being used, TXD(48) converts the N-bytes of data starting at S to ASCII, adds the Host Link header, FCS, and terminator, and transmits this data as a Host Link frame.
Page 271: No-Protocol Communications
RS-232C port to a host computer. If AR 0805 (the RS-232C Transmit Ready Flag) is ON when IR 00100 turns ON, the ten bytes of data (DM 0100 to DM 0104) will be transmitted to the host computer, leftmost bytes first.
Page 272 Data (256 bytes max.) Note 1. The start and end codes are set in DM 6648 to DM 6649 (RS-232C) or DM 6653 to DM 6654 (peripheral port) in the PC Setup. 2. When there are several start or end codes in the transmission, the first of each will be effective.
Page 273 Continually available for reception Start code enabled: After start code is received Reception Complete: When either the end code, the specified no. of bytes, or 256 bytes are received. Application Procedure Setting the Communications switch Set the CPM2A CPU Unit’s communications switch or the CPM2C CPU Unit’s DIP switch.
Page 274 Note An RS-232C Adapter is needed to perform no-protocol communications through the peripheral port. Connecting the Cables This section describes RS-232C connections. The RS-232C port on the serial device and the RS-232C port of the CPM2A/ CPM2C or CPM1-CIF01 RS-232C Adapter are connected as shown in the fol-...
Page 275 0: LR 00 to LR 15; Other: Not effective 12 to 15 Communications mode 0: Host Link; 1: No-protocol; 2: 1:1 PC Link Slave; 3: 1:1 PC Link Master; 4: 1:1 NT Link (Other settings will cause a non-fatal error, the Host Link setting will be used, and...
Page 276 (No-protocol, effective when bits 12 to 15 of DM 6648 are set to 1.) Note If SW1 on the front panel of the CPU Unit is ON, the RS-232C port will operate with the default settings regardless of the settings in DM 6645 to DM 6649.
Page 277 (Peripheral port, effective when bits 12 to 15 of DM 6653 are set to 1) Note 1. If SW1 on the front panel of the CPU Unit is ON, the peripheral port will oper- ate with the default settings regardless of the settings in DM 6645 to DM 6649.
Page 278 TXD(48) is used to transmit data to RS-232C devices. (@)TXD(48) S: Leading address of data to be transmitted C: Control data N: Number of bytes to be transmitted (BCD: 0001 to 0256) Storage order 0: Leftmost bytes first 1: Rightmost bytes first Communications port...
Page 279 DM 0100 to DM 0104 is transmitted from leftmost bytes to right- most bytes. When AR 0806 (the Reception Completed Flag) turns ON, 256 by- tes of received data are read and written to DM 0200 from leftmost bytes to right- most bytes.
Page 280: One-To-One Nt Link Communications
The NT Link allows a CPM2A/CPM2C PC to be connected directly to an OMRON Programmable Terminal. There is no need for a communications pro- gram on the PC. The NT Link can be used with an RS-232C port. CPM2A Connection...
Page 281 Use the settings in the PC Setup (DM6645 to DM 6649) for Setting communications. RS-232C communications. (Turn OFF the Communications switch on the CPM2A’s CPU Unit or pin 1 of the DIP Switch on the CPM2C’s CPU Unit.) Connecting the cables Connect to a Programmable Terminal. Communications Switch The CPM2A’s communications are controlled by the communications switch on...
Page 282 RS-232C port CPM2C DIP Switch Settings Turn OFF pin 1 of the DIP switch when using 1:1 NT Link communications so that communications through the RS-232C port are governed by the settings in the PC Setup (DM 6645 to DM 6649).
Page 283: One-To-One Pc Link Communications
Hood 4-3-4 One-to-one PC Link Communications A 1:1 PC Link of up to 256 bits (LR0000 to LR1515) can be created with the data area of another CPM2A/CPM2C, CQM1, CPM1, CPM1A, SRM1(-V2), or a C200HX/HG/HE PC, where one serves as the Master, the other as a Slave.
Page 284 CPM2A/CPM2C Communications Functions Section One-to-one PC Link CPM2A CPU Unit CPM2A CPU Unit RS-232C port RS-232C port OMRON PC (CQM1, CPM1, CPM1A, CPM2C, OMRON PC (CQM1, CPM1, CPM1A, CPM2C, SRM1(-V2), C200HS, or C200HX/HG/HE) SRM1(-V2), C200HS, or C200HX/HG/HE)
Page 285 LR00 Write Read Write Read area area LR07 LR07 LR08 LR08 Read Write Read Write area area LR15 LR15 Note Even though the peripheral port on the CPM2C-CIF01-V1 can output RS-232C, this port cannot be used for one-to-one link communications.
Page 286 Section PC Links with Other PCs The link relay area on CPM2A/CPM2C PCs is only 16 words, LR00 to LR15. When performing a 1:1 PC Link with a CPM2A/CPM2C PC and a CQM1, C200HS, or C200HX/HE/HG use the corresponding 16 words, LR00 to LR15 on the CQM1, C200HS, or C200HX/HE/HG PC.
Page 287 Section CPM2C DIP Switch Settings Turn OFF pin 1 of the DIP switch when using 1:1 PC Link communications so that communications through the RS-232C port are governed by the settings in the PC Setup (DM 6645 to DM 6649).
Page 288: Srm1(-V2) Communications Functions
SRM1(-V2) Communications Functions Section PC Setup When creating a 1:1 PC Link with a CPM2A/CPM2C PC, use a Programming Device to make the following settings to the PC Setup (DM 6645) in the Master and Slave. Word Function Master Slave...
Page 289 (Other settings will cause a non-fatal error, the default setting (0000) will be used, and AR 1302 will turn ON.) 08 to 11 Start code enable (RS-232C, effective when bits 12 to 15 of DM 6650 are set to 1.) 0: Disable 1: Set 12 to 15 End code enable (RS-232C, effective when bits 12 to 15 of DM 6650 are set to 1.)
Page 290 12 to 15 Communications mode 0: Host Link; 1: No-protocol; 2: 1:1 PC Link Slave; 3: 1:1 PC Link Master; 4: 1:1 NT Link; 5: 1:N NT Link (Any other setting specifies Host Link mode, causes a non-fatal error, and turns ON AR 1302.)
Page 291 Function Setting DM 6648 00 to 07 Node number (Host Link, effective when bits 12 to 15 of DM 6645 are set to 0.) 00 to 31 00 to 31 (BCD) 08 to 11 Start code enable (RS-232C, effective when bits 12 to 15 of DM 6645 are set to 1.) 0: Disable;...
Page 292: No-Protocol Communications
256 bytes, N will be between 254 and 256 depending on the desig- nations for start and end codes. If the number of bytes to be sent is set to 0000, only the start and end codes will be sent.
Page 293 To reset the peripheral port, turn ON SR 25208. These bits will turn OFF auto- matically after the reset. The start code and end code are not included in AR 09 or AR 10 (number of bytes received). The data will be as follows: “31323132313231323132CR LF”...
Page 294 (Other settings will cause a non-fatal error, the default setting (0000) will be used, and AR 1302 will turn ON.) 08 to 11 Start code enable (RS-232C, effective when bits 12 to 15 of DM 6650 are set to 1.) As re- 0: Disable...
Page 295 12 to 15 Communications mode 0: Host Link; 1: No-protocol; 2: 1:1 PC Link Slave; 3: 1:1 PC Link Master; 4: 1:1 NT Link; 5: 1:N NT Link (Any other setting specifies Host Link mode, causes a non-fatal error, and turns ON AR 1302.)
Page 296 Data (256 bytes max.) Note 1. The start and end codes are set in DM 6648 to DM 6649 and DM 6653 to DM 6654 of the PC Setup. 2. When there are several start and end codes, the first part of each will be ef- fective.
Page 297: One-To-One Nt Link Communications
SRM1(-V2) Communications Functions Section Reception Complete: When either the end code, the specified no. of bytes, or 256 bytes are received. Program Example The following program example is for no-protocol communication conducted through a RS-232C port using TXD(48) and RXD(47) instructions.
Page 298: One-To-N Nt Link Communications
The 1:N NT Link is supported by SRM1-C02-V2 only. 12 to 15 Communications mode 0: Host Link; 1: No-protocol; 2: 1:1 PC Link Slave; 3: 1:1 PC Link Master; 4: 1:1 NT Link; 5: 1:N NT Link The 1:N NT Link is supported by SRM1-C02-V2 only.
Page 299: One-To-One Pc Link Communications
The 1:N NT Link is supported by SRM1-C02-V2 only. 12 to 15 Communications mode 0: Host Link; 1: No-protocol; 2: 1:1 PC Link Slave; 3: 1:1 PC Link Master; 4: 1:1 NT Link; 5: 1:N NT Link The 1:N NT Link is supported by SRM1-C02-V2 only.
Page 300 RS-232C port. Only the 16 LR words from LR 00 to LR 15 can be linked in the SRM1, so use only those 16 words in the CQM1 or C200HS when making a 1:1 PC Link with one of those PCs.
Page 301: Host Link Commands
1. Words 0050 to 0199 cannot be specified in CPM2A/CPM2C PCs and words 0020 to 0199 cannot be specified in CPM1/CPM1A/SRM1(-V2) PCs. If an attempt to read any of these words is made, a response of 0000 will be re- turned.
Page 302: Lr Area Read - Rl
Host Link Commands Section 4-5-2 LR AREA READ – RL Reads the contents of the specified number of LR words, starting from the speci- fied word. Command Format x 10 x 10 x 10 x 10 x 10 x 10...
Page 303: Tc Status Read - Rg
Parameters Read Data (Response) The number of present values specified by the command is returned in hexade- cimal as a response. The PVs are returned in order, starting with the specified beginning timer/counter. 4-5-5 TC STATUS READ – RG Reads the status of the Completion Flags of the specified number of timers/ counters, starting from the specified timer/counter.
Page 304: Ar Area Read - Rj
1. Words DM 1024 to DM 6143 in CPM1/CPM1A PCs and words DM 2048 to DM 6143 in CPM2A/CPM2C/SRM1(-V2) PCs cannot be specified. If an at- tempt to read any of these words is made, a response of 0000 will be re- turned.
Page 305: Ir/Sr Area Write - Wr
Parameters Write Data (Command) Specify in order the contents of the number of words to be written to the IR or SR area in hexadecimal, starting with the specified beginning word. Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
Page 306: Hr Area Write - Wh
Parameters Write Data (Command) Specify in order the contents of the number of words to be written to the LR area in hexadecimal, starting with the specified beginning word. Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
Page 307: Tc Status Write - Wg
Note 1. When this command is used to write data to the PV area, the Completion Flags for the timers/counters that are written will be turned OFF. 2. If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
Page 308: Dm Area Write - Wd
Parameters Write Data (Command) Specify in order the contents of the number of words to be written to the DM area in hexadecimal, starting with the specified beginning word. Note 1. If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
Page 309: Sv Read 1 - R
Parameters Write Data (Command) Specify in order the contents of the number of words to be written to the AR area in hexadecimal, starting with the specified beginning word. Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed.
Page 310: Sv Read 2 - R
Note 1. The instruction specified under “Name” must be in four characters. 2. If the same instruction is used more than once in a program, only the first one will be read. 3. Use this command only when it is definite that a constant SV has been set.
Page 311: Sv Change 1 - W
REVERSIBLE COUNTER Operand, SV (Response) The name that indicates the SV classification is returned to “Operand,” and ei- ther the word address where the SV is stored or the constant SV is returned to “SV.” Operand Constant or word address...
Page 312: Sv Change 2 - W
10 x 10 x 10 x 10 Operand Terminator Note TC number: 0000 to 0255 in CPM2A/CPM2C PCs and 0000 to 0127 in CPM1/CPM1A/SRM1(-V2) PCs Response Format An end code of 00 indicates normal completion. x 10 x 10...
Page 313: Status Read - Ms
Section Operand, SV (Response) In “Operand,” specify the name that indicates the SV classification. Specify the name in four characters. In “SV,” specify either the word address where the SV is stored or the constant SV. Operand Constant or word address...
Page 314: Status Write - Sc
Section Parameters Status Data, Message (Response) “Status data” consists of four digits (two bytes) hexadecimal. The leftmost byte indicates CPU Unit operation mode, and the rightmost byte indicates the size of the program area. x 16 x 16 15 14 13 12...
Page 315: Error Read - Mf
(2nd word) Parameters Error Clear (Command) Specify 01 to clear errors and 00 to not clear errors (BCD). Fatal errors can be cleared only when the PC is in PROGRAM mode. Error Information (Response) The error information comes in two words.
Page 316 ON: Cycle time overrun (Error code F8) 4-5-22 FORCED SET – KS Force sets a bit in the IR, SR, LR, HR, AR, or TC area. Just one bit can be force set at a time. Once a bit has been forced set or reset, that status will be retained until a FORCED SET/RESET CANCEL (KC) command or the next FORCED SET/RE- SET command is transmitted.
Page 317: Forced Reset - Kr
4-5-23 FORCED RESET – KR Force resets a bit in the IR, SR, LR, HR, AR, or TC area. Just one bit can be force reset at a time.
Page 318: Multiple Forced Set/Reset - Fk
Parameters Name, Word address, Bit (Command) In “Name,” specify the area (i.e., IR, SR, LR, HR, AR, or TC) that is to be forced reset. Specify the name in four characters. In “Word address,” specify the ad- dress of the word, and in “Bit” the number of the bit that is to be forced reset.
Page 319: Forced Set/Reset Cancel - Kc
Parameters Name, Word address (Command) In “Name,” specify the area (i.e., IR, SR, LR, HR, AR, or TC) that is to be forced set or reset. Specify the name in four characters. In “Word address,” specify the address of the word that is to be forced set or reset.
Page 320: Pc Model Read - Mm
C2000 C1000H C2000H/CQM1/CPM2A/CPM2C/CPM1/CPM1A/SRM1(-V2) C20H/C28H/C40H/C200H/C200HS CV500 CV1000 CV2000 CVM1-CPU01-E CVM1-CPU11-E CVM1-CPU21-E 4-5-27 TEST – TS Returns, unaltered, one block of data transmitted from the host computer. Command Format x 10 x 10 122 characters max. Terminator Node no. Header Characters code...
Page 321: Program Read - Rp
4-5-28 PROGRAM READ – RP Reads the contents of the PC user’s program area in machine language (object code). The contents are read as a block, from the beginning to the end. Command Format x 10 x 10 Node no.
Page 322: Compound Command - Qq
Host Link Commands Section 4-5-30 COMPOUND COMMAND – QQ Registers at the PC all of the bits, words, and timers/counters that are to be read, and reads the status of all of them as a batch. Registering Read Information Register the information on all of the bits, words, and timers/counters that are to be read.
Page 323 Section Read Word address, Data Format (Command) Depending on the area and type of data that are to be read, the information to be read is as shown in the following table. The “read data” is specified in four digits BCD, and the data format is specified in two digits BCD.
Page 324: Abort - Xz
Parameters Read Data (Response) Read data is returned according to the data format and the order in which read information was registered using QQ. If “Completion Flag” has been specified, then bit data (ON or OFF) is returned. If “Word” has been specified, then word data is returned.
Page 325: Undefined Command - Ic
Characters (Response) This is the data specified in TXD(48) that has been converted to ASCII. 4-5-34 Undefined Command – IC This response is returned if the header code of a command cannot be decoded. Check the header code. Response Format...
Page 326: Memory Areas
SECTION 5 Memory Areas This section describes the structure of the PC memory areas and explains how to use them. Memory Area Functions ........... .
Page 327: Memory Area Functions
(56 words) trol PC operation. Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, AR area, Counter area, and read/write DM area are backed up by a capacitor. The backup time varies with the ambient temperature, but at 25_C, the capacitor will back up memory for 20 days.
Page 328: Section 5 Memory Areas
(56 words) trol PC operation. Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, AR area, Counter area, and read/write DM area are backed up by the CPU Unit’s battery. If the battery is removed or fails, the contents of these areas will be lost and returned to default values.
Page 329 (56 words) trol PC operation. Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, AR area, Counter area, and read/write DM area are backed up by a capacitor or a battery. Refer to 2-1-2 Characteristics in the SRM1 Master Control Unit Operation Manual for a graph showing the backup time vs.
Page 330: Functions
IR 01915 are allocated to terminals on the CPU Unit and Expansion I/O Units. With the SRM1(-V2), IR area bits from IR 00000 to IR 00715 and IR 01000 to IR 01715 are allocated to CompoBus/S Slaves. They reflect the ON/OFF status of input and output signals.
Page 331 TC numbers are used to create timers and counters, as well as to access Completion Flags and present values (PVs). If a TC number is designated for word data, it will access the present value (PV); if it is used for bit data, it will ac- cess the Completion Flag for the timer/counter.
Page 332: I/O Allocation For Cpm1/Cpm1A/Cpm2A Pcs
CPM1/CPM1A/SRM1(-V2) PCs. Writing Data In order to write the contents of the UM area, the DM read-only area (DM 6144 to DM 6599, and the PC Setup area (DM 6600 to DM 6655) to the flash memory, either one of the following operations must be performed.
Page 333 1. The values for the maximum number of I/O in the above table include I/O on Expansion I/O Units. 2. When using a CPM1A CPU Unit with 30 or 40 I/O points, up to 3 Expansion Units or Expansion I/O Units can be connected to the PC.
Page 334 Input bits are allocated starting from IR 00000. Output bits are allocated starting from IR 01000. Bits in the output words that are not used as output bits can be used as work bits. Bits in the input words that are not used as input bits cannot be used as work bits.
Page 335 I/O Allocation for CPM1/CPM1A/CPM2A PCs Section CPU Units with 20 I/O Points 12 inputs CPM1-20CDR-j IR 00000 to IR 00011 CPM1A-20CDj-j CPM2A-20CDj-j 8 outputs IR 01000 to IR 01007 Bits Inputs IR 000 Do not use Outputs IR 010 CPU Units with 30 I/O Points...
Page 336: Expansion I/O Units
8 outputs: Word (n+1), bits 00 to 07 CPM1-30CDR-j(-V1) Note m: “m” denotes the last input word allocated to the CPU Unit, or to the previous Expansion Unit or Expansion I/O Unit if one is already connected. n: “n” denotes the last output word allocated to the CPU Unit, or to the previous Expansion Unit or Expansion I/O Unit if one is already connected.
Page 337: Expansion Units
Li k U i Link Unit CPM2A CPM2A Output 32 bits: n+1, n+2 Note 1. m: “m” denotes the last input word allocated to the CPU Unit, or to the pre- vious Expansion Unit or Expansion I/O Unit if one is already connected.
Page 338: Examples Of Expansion Unit And Expansion I/O Unit Allocation
Output: word (n+1) Output: word (n+1, n+2) Note Input bits 00 to 07 in word (m+1) are for outputs from the Master. Output bits 00 to 07 in word (n+1), are for inputs to the Master. 5-2-4 Examples of Expansion Unit and Expansion I/O Unit Allocation When using a CPM1 CPU Unit without “-V1”...
Page 339 IR 01000 to IR 01007 and IR 01100 to IR 01107 are allocated as output bits. IR 01108 to IR 01115 can be used as work bits. IR 002 to IR 009 of the input words and IR 012 to IR 019 of the output words can all be used as work words.
Page 340 I/O Allocation for CPM1/CPM1A/CPM2A PCs Section Example: CPU Unit with 60 I/O Points + 3 Expansion I/O Units CPU Unit Expansion I/O Unit Expansion I/O Unit Expansion I/O Unit (60 I/O points) (20 I/O points) (16 outputs) (20 I/O points)
Page 341 I/O Allocation for CPM1/CPM1A/CPM2A PCs Section Example: Configuration Including Analog I/O Unit, Temperature Sensor Unit, and Expansion I/O Unit CPU Unit Analog I/O Unit Temperature Sensor Unit Expansion I/O Unit (60 I/O points) CPM1A-MAD01/11 CPM1A-TS001/101 (20 I/O points) 36 inputs...
Page 342: I/O Allocation For Cpm2C Pcs
01100 to 01107 Note 1. The values for the maximum number of I/O in the above table include the I/O on Expansion I/O Units. 2. Although only up to 5 Expansion Units or Expansion I/O Units can be con- nected to a CPM2C PC, no more than 10 input words and 10 output words can be allocated.
Page 343 Input bits are allocated starting from IR 00000. Output bits are allocated starting from IR 01000. Bits in the output words that are not used as output bits can be used as work bits. Bits in the input words that are not used as input bits cannot be used as work bits.
Page 344: Expansion I/O Units
Output 16 outputs: Word (n+1), bits 00 to 15 Note m: “m” denotes the last input word allocated to the CPU Unit, or to the previous Expansion Unit or Expansion I/O Unit if one is already connected. n: “n” denotes the last output word allocated to the CPU Unit, or to the previous Expansion Unit or Expansion I/O Unit if one is already connected.
Page 345 Bits in the output words that are not used as output bits can be used as work bits. Bits in the input words that are not used as input bits can be used as work bits. Expansion I/O Unit with 8 Inputs...
Page 346 I/O Allocation for CPM2C PCs Section Expansion I/O Unit with 10 I/O Points 6 inputs CPM2C-10EDR Word (m+1), bit 00 Word (m+1), bit 05 4 outputs Word (n+1), bit 00 Word (n+1), bit 03 Bits Inputs Do not use Outputs...
Page 347: Expansion Units
1 output: n+1 Note 1. m: “m” denotes the last input word allocated to the CPU Unit, or to the pre- vious Expansion Unit or Expansion I/O Unit if one is already connected. “n” denotes the last output word allocated to the CPU Unit, or to the pre- vious Expansion Unit or Expansion I/O Unit if one is already connected.
Page 348: Examples Of Expansion Unit And Expansion I/O Unit Allocation
8 outputs Output: word (n+1) Note Input bits 00 to 07 in word (m+1) are for outputs from the Master. Output bits 00 to 07 in word (n+1), are for inputs to the Master. 5-3-4 Examples of Expansion Unit and Expansion I/O Unit Allocation Up to 5 Expansion Units or Expansion I/O Units can be connected to a CPM2C PC.
Page 349 I/O Allocation for CPM2C PCs Section Example: CPU Unit with 32 I/O Points + 5 Expansion I/O Units with 32 I/O Points CPU Unit Expansion I/O Unit Expansion I/O Unit Expansion I/O Unit Expansion I/O Unit Expansion I/O Unit (32 I/O points)
Page 350 I/O Allocation for CPM2C PCs Section Example: Configuration Including Analog I/O Units, Temperature Sensor Units, and Expansion I/O Unit CPU Unit Analog I/O Unit 1 Temperature Sensor Analog I/O Unit 2 Temperature Sensor Expansion I/O Unit (20 I/O points) CPM2C-MAD11...
Page 351: Ladder-Diagram Programming
This section explains the basic steps and concepts involved in writing a basic ladder diagram program. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution. The entire set of instruc- tions used in programming is described in Section 7 Instruction Set.
Page 352: Basic Procedure
A bit whose address is designated as an operand is called an operand bit; a word whose address is designated as an operand is called an operand word. If the actual value is entered as a constant, it is preceded by # to indicate that it is not an address.
Page 353: Basic Ladder Diagrams
A ladder diagram consists of one line running down the left side with lines branching off to the right. The line on the left is called the bus bar; the branching lines, instruction lines or rungs. Along the instruction lines are placed conditions that lead to other instructions on the right side.
Page 354 The operands designated for any of the ladder instructions can be any bit in the IR, SR, HR, AR, LR, or TC areas. This means that the conditions in a ladder dia- gram can be determined by I/O bits, flags, work bits, timers/counters, etc. LOAD and OUTPUT instructions can also use TR area bits, but they do so only in spe- cial applications.
Page 355 When converting to mnemonic code, all but ladder diagram instruc- tions are written in the same form, one word to a line, just as they appear in the ladder diagram symbols. An example of mnemonic code is shown below. The instructions used in it are described later in the manual.
Page 356 The instruction would have an ON execution condition only when all three condi- tions are ON, i.e., when IR 00000 was ON, IR 00100 was OFF, and LR 0000 was AND instructions in series can be considered individually, with each taking the logical AND of the execution condition (i.e., the total of all conditions up to that...
Page 357 NOT instruction; the rest of the conditions correspond to OR or OR NOT instruc- tions. The following example shows three conditions which correspond in order from the top to a LOAD NOT, an OR NOT, and an OR instruction. Again, each of these instructions requires one line of mnemonic code.
Page 358 In the above examples, IR 01000 will be ON as long as IR 00000 is ON and IR 01001 will be OFF as long as IR 00001 is ON. Here, IR 00000 and IR 00001 would be input bits and IR 01000 and IR 01001 output bits assigned to the Units controlled by the PC, i.e., the signals coming in through the input points assigned...
Page 359 The last instruction required to complete a simple program is the END instruc- tion. When the CPU Unit scans the program, it executes all instructions up to the first END instruction before returning to the beginning of the program and begin- ning execution again.
Page 360 OR between IR 00000 and IR 00001 is attempted, the OR NOT be- tween IR 00002 and IR 00003 is lost and the OR NOT ends up being an OR NOT between just IR 00003 and the result of an AND between IR 00002 and the first OR.
Page 361 With both AND LOAD and OR LOAD there are two ways to achieve this. One is to code the logic block instruction after the first two blocks and then after each additional block. The other is to code all of the blocks to be combined, starting each block with LOAD or LOAD NOT, and then to code the logic block instructions which combine them.
Page 362 00008 20001 Again, with the method on the right, a maximum of eight blocks can be com- bined. There is no limit to the number of blocks that can be combined with the first method. Combining AND LOAD and Both of the coding methods described above can also be used when using AND...
Page 363 These blocks are then coded, combining the small blocks first, and then combining the larger blocks. Either AND LOAD or OR LOAD is used to combine the blocks, i.e., AND LOAD or OR LOAD always combines the last two execution conditions that existed, regard- less of whether the execution conditions resulted from a single condition, from logic blocks, or from previous logic block instructions.
Page 364 The following type of diagram can be coded easily if each block is coded in order: first top to bottom and then left to right. In the following diagram, blocks a and b would be combined using AND LOAD as shown above, and then block c would be coded and a second AND LOAD would be used to combined it with the execu- tion condition from the first AND LOAD.
Page 365 Basic Ladder Diagrams Section The following diagram requires an OR LOAD followed by an AND LOAD to code the top of the three blocks, and then two more OR LOADs to complete the mne- monic code. 00000 00001 Address Instruction...
Page 366 The first logic block instruction is used to combine the execution conditions re- sulting from blocks a and b, and the second one is to combine the execution condition of block c with the execution condition resulting from the normally closed condition assigned IR 00003.
Page 367 This is because instruction lines are executed across to a right-hand instruction before returning to the branching point to execute instructions one a branch line. If a condition exists on any of the instruc- tion lines after the branching point, the execution condition could change during this time making proper execution impossible.
Page 368 TR 1 is loaded for an AND with the status IR 00003. The execution condition stored in TR 0 is loaded twice, the first time for an AND with the status of IR 00004 and the second time for an AND with the inverse of the status of IR 00005.
Page 369 Basic Ladder Diagrams Section TR bits can be used as many times as required as long as the same TR bit is not used more than once in the same instruction block. Here, a new instruction block is begun each time execution returns to the bus bar. If, in a single instruction...
Page 370 00006 ILC(03) If IR 00000 is ON in the revised version of diagram B, above, the status of IR 00001 and that of IR 00002 would determine the execution conditions for instructions 1 and 2, respectively. Because IR 00000 is ON, this would produce the same results as ANDing the status of each of these bits.
Page 371 Although 01 has been used as the jump number, any number between 01 and 99 could be used as long as it has not already been used in a different part of the program. JUMP and JUMP END require no other operand and JUMP END never has conditions on the instruction line leading to it.
Page 372: Controlling Bit Status
Although these instructions are used to turn ON and OFF output bits in the IR area (i.e., to send or stop output signals to external devices), they are also used to control the status of other bits in the IR area or in other data areas.
Page 373 DIFD(14) 20002 Here, IR 20001 will be turned ON for one cycle after IR 00000 goes ON. The next time DIFU(13) 20001 is executed, IR 20001 will be turned OFF, regardless of the status of IR 00000. With the DIFFERENTIATE DOWN instruction, IR 20002 will be turned ON for one cycle after IR 00001 goes OFF (IR 20002 will be kept OFF until then), and will be turned OFF the next time DIFD(14) 20002 is executed.
Page 374: Work Bits (Internal Relays)
Work Bits (Internal Relays) Section In the following example, HR 0000 will be turned ON when IR 00002 is ON and IR 00003 is OFF. HR 0000 will then remain ON until either IR 00004 or IR 00005 turns ON. With KEEP, as with all instructions requiring more than one instruction line, the instruction lines are coded first before the instruction that they control.
Page 375 UP, DIFFERENTIATE DOWN, and KEEP instructions. The work bit is used first as the operand for one of these instructions so that later it can be used as a condition that will determine how other instructions will be executed. Work bits can also be used with other instructions, e.g., with the SHIFT REGISTER...
Page 376: Programming Precautions
IR 20000 must be left ON continuously as long as IR 001001 is ON and both IR 00002 and IR 00003 are OFF, or as long as IR 00004 is ON and IR 00005 is OFF. It must be turned ON for only one cycle each time IR 00000 turns ON (un- less one of the preceding conditions is keeping it ON continuously).
Page 377 Again, diagram A , below, must be drawn as diagram B. If an instruc- tion must be continuously executed (e.g., if an output must always be kept ON while the program is being executed), the Always ON Flag (SR 25313) in the SR area can be used.
Page 378: Program Execution
Program execution is only one of the tasks carried out by the CPU Unit as part of the cycle time. Refer to Section 8 PC Operations and Processing Time for de-...
Page 379: Instruction Set
Some instructions, such as Timer and Counter instructions, are used to control execution of other instructions, e.g., a TIM Completion Flag might be used to turn ON a bit when the time period set for the timer has expired. Although these other instructions are often used to control output bits through the Output instruction, they can be used to control execution of other instructions as well.
Page 380 ..........7-18-2 SIGNED BINARY TO BCD SCALING – SCL2(––) .
Page 381 ......7-27-4 PULSE WITH VARIABLE DUTY RATIO – PWM(––) ....
Page 382: Notation
The border between the IR and SR areas can, howev- er, be crossed for a single operand, i.e., the last bit in the IR area may be speci- fied for an operand that requires more than one word as long as the SR area is...
Page 383 DM area. In the above example, the content of DM 0001 has to be in BCD and has to specify an address in the DM area of the PC being used. (Refer to Section 5 Memory Areas for DM area details.)
Page 384: Differentiated Instructions
DIFD(14). DIFU(13) operates the same as a differentiated instruction, but is used to turn ON a bit for one cycle. DIFD(14) also turns ON a bit for one cycle, but does it when the execution condition has changed from ON to OFF. Refer to...
Page 385: Coding Right-Hand Instructions
If an IR or SR address is used in the data column, the left side of the column is left blank. If any other data area is used, the data area abbreviation is placed on the left side and the address is placed on the right side.
Page 386 Coding Right-hand Instructions Section The following diagram and corresponding mnemonic code illustrates the points described previously. Address Instruction Data 00000 00001 DIFU(13) 21600 00000 00000 00002 00001 00001 00002 00002 00003 DIFU(13) 21600 00100 00200 21600 BCNT(67) 00004 00100 01001 01002...
Page 387 Each of the lines for the instruction is coded, starting with LD or LD NOT, to form ‘logic blocks’ that are combined by the right-hand instruction. An example of this for SFT(10) is shown below.
Page 388: Instruction Tables
The following table lists the CPM1/CPM1A instructions that have fixed function codes. Each instruction is listed by mnemonic and by instruction name. Use the numbers in the leftmost column as the left digit and the number in the column heading as the right digit of the function code.
Page 389 Each instruction is listed by mnemonic and by instruction name. Use the numbers in the leftmost column as the left digit and the number in the column heading as the right digit of the function code.
Page 390 The following table lists the SRM1(-V2) instructions that have fixed function codes. Each instruction is listed by mnemonic and by instruction name. Use the numbers in the leftmost column as the left digit and the number in the column heading as the right digit of the function code.
Page 391 “None” indicates instructions for which function codes are not used. In the CPU Units column, “SRM1” indicates all versions of the SRM1 CPU Units and “SRM1(-V2)” indicates only version 2 of the SRM1 CPU Units. Mnemonic...
Page 392 CPM2A/CPM2C/SRM1(-V2) PRV (@) HIGH-SPEED COUNTER PV READ All except SRM1 PULS (@) SET PULSES CPM1A/CPM2A/CPM2C (Transistor outputs only) PWM (@) –– PULSE WITH VARIABLE DUTY RATIO CPM2A/CPM2C SUBROUTINE RETURN ROL (@) ROTATE LEFT ROR (@) ROTATE RIGHT RSET None RESET...
Page 393 Section Mnemonic Code Words Name CPU Units Page SHIFT REGISTER SFTR (@) REVERSIBLE SHIFT REGISTER SLD (@) ONE DIGIT SHIFT LEFT SNXT STEP START SPED (@) SPEED OUTPUT CPM1A/CPM2A/CPM2C (Transistor outputs only) SRCH (@) –– DATA SEARCH CPM2A/CPM2C SRD (@)
Page 394: Ladder Diagram Instructions
IR, SR, AR, HR, TC, LR Limitations There is no limit to the number of any of these instructions, or restrictions in the order in which they must be used, as long as the memory capacity of the PC is not exceeded. Description These six basic instructions correspond to the conditions on a ladder diagram.
Page 395: Bit Control Instructions
AND LD and OR LD logically combine two execution conditions, the current one and the last unused one. In order to draw ladder diagrams, it is not necessary to use AND LD and OR LD instructions, nor are they necessary when inputting ladder diagrams directly, as is possible from the SSS.
Page 396 This is particularly helpful and allows a complex set of conditions to be used to control the status of a single work bit, and then that work bit can be used to control other instructions.
Page 397 Bit Control Instructions Section In the second example (Diagram B), IR 10000 will be turned ON when IR 00001 goes ON and will remain ON (even if IR 00001 goes OFF) until IR 00002 goes 00000 Address Instruction Operands 20000...
Page 398 ON and the current execution condition is either ON or OFF, DIFU(13) will either turn the designated bit OFF or leave it OFF (i.e., if the desig- nated bit is already OFF). The designated bit will thus never be ON for longer than one cycle, assuming it is executed each cycle (see Precautions, below).
Page 399: No Operation - Nop
7-29-1 INTERRUPT CONTROL – INT(89). Example In this example, IR 20014 will be turned ON for one cycle when IR 00000 goes from OFF to ON. IR 20015 will be turned ON for one cycle when IR 00000 goes from ON to OFF. 00000...
Page 400 HR, and SR bits and words written to as operands in the instructions are turned OFF. IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be used several times in a row, with each IL(02) creating an interlocked section through the next ILC(03).
Page 401: Jump And Jump End - Jmp(04) And Jme
00013 ILC(03) When the execution condition for the first IL(02) is OFF, TIM 000 will be reset to 1.5 s, CNT 001 will not be changed, and 01002 will be turned OFF. When the execution condition for the first IL(02) is ON and the execution condition for the second IL(02) is OFF, TIM 000 will be executed according to the status of 00001, CNT 001 will not be changed, and 01002 will be turned OFF.
Page 402 7-12 Jump Number 00 If the jump number for JMP(04) is 00, the CPU Unit will look for the next JME(05) with a jump number of 00. To do so, it must search through the program, causing a longer cycle time (when the execution condition is OFF) than for other jumps.
Page 403: User Error Instructions: Failure Alarm And Reset - Fal(06) And Severe Failure Alarm - Fals
ON execution condition, either of these instructions will output a FAL number to bits 00 to 07 of SR 253. The FAL number that is output can be be- tween 01 and 99 and is input as the definer for FAL(06) or FALS(07). FAL(06) with a definer of 00 is used to reset this area (see below).
Page 404 (i.e., END(01), IL(02)/ILC(03), JMP(04)/JME(05), and SBN(92)) may not be included. STEP(08) uses a control bit in the IR or HR areas to define the beginning of a section of the program called a step. STEP(08) does not require an execution condition, i.e., its execution is controlled through the control bit.
Page 405 OFF the control bit for the step (see example 3 below). When the step is completed, all of the IR and HR bits in the step are turned OFF and all timers in the step are reset to their SVs. Counters, shift registers, and bits used in KEEP(11) maintain status.
Page 406: Timer And Counter Instructions
(PV) of the timer or counter. The PV of a timer or counter can thus be used as an operand in CMP(20), or any other instruction for which the TC area is allowed. This is done by designating the TC number used to define that timer or counter to access the memory location that holds the PV.
Page 407 The same is true of all other TC numbers prefixed with TIM or CNT. An SV can be input as a constant or as a word address in a data area. If an IR area word assigned to an Input Unit is designated as the word address, the Input Unit can be wired so that the SV can be set externally through thumbwheel switches or similar devices.
Page 408 The timer will not work properly if it is not reset. If the timer’s set value is set to 0000, the Completion Flag will turn ON as soon as the timer’s execution condition turns ON. If the timer’s set value is set to 0001, the Completion Flag will turn ON somewhere between 0 and 0.1 s after the tim-...
Page 409 TIMH(15) if they are required for TMHH(––). Refer to 7-15-3 VERY HIGH- SPEED TIMER – TMHH(––) for details. If the timer’s set value is set to 0000, the Completion Flag will turn ON as soon as the timer’s execution condition turns ON. If TIM000 to TIM003 are used, howev- er, there may be a delay before the flag turns ON.
Page 410 Very high-speed timers in interlocked program sections are reset (to the SV) when the execution condition for IL(02) is OFF. If the timer’s set value is set to 0000, the Completion Flag will turn ON as soon as the timer’s execution condition turns ON. If TIM004 to TIM007 are used, howev- er, there may be a delay before the flag turns ON.
Page 411 TIML(––) is a decrementing ON-delay timer that can time in 1-s units or 10-s units. The timer set value can be 0 to 9,999 s (accuracy 0 to 1 s) when 1-s units are used (C=000) or 0.10 to 99,990 s (accuracy 0 to 10 s) when 10-s units are used (C=001).
Page 412 ON until the counter is reset. CNT is reset with a reset input, R. When R goes from OFF to ON, the PV is reset to SV. The PV will not be decremented while R is ON. Counting down from SV will begin again when R goes OFF.
Page 413 CNTR(12) is executed with an ON execution condition for DI and the last execu- tion condition for DI was OFF. If OFF to ON changes have occurred in both II and DI since the last execution, the PV will not be changed.
Page 414 When decremented from 0000, the present value is set to SV and the Comple- tion Flag is turned ON until the PV is decremented again. When incremented past the SV, the PV is set to 0000 and the Completion Flag is turned ON until the PV is incremented again.
Page 415 Registers a target value comparison table. Start comparison with INI(61). Registers a range comparison table. Start comparison with INI(61). Note If C is set to 000 or 001, CTBL(63) will continue the comparison operation even when executed only once. As a rule, use the differentiated form (@) of the instruction or an input condition that turns ON for only one cycle.
Page 416 Subroutine number (See note 2.) Note 1. Each range’s lower limit must be less than its upper limit. An error will occur if the lower limit is greater than the upper limit. 2. The subroutine number can be 0000 to 0049 and the subroutine will be exe- cuted as long as the counter’s PV is within the specified range.
Page 417 Limitations In the CPM1/CPM1A PCs, P must be 000 and C must be 000 to 003. In CPM2A/CPM2C PCs, P must be 000, 010, 100, 101, 102, or 103 and C must be 000 to 005. P1 must be 000 unless C is 002 or 004.
Page 418 P1+1. The PV cannot be changed while the pulse output is in progress. The new PV can be –16,777,215 to 16,777,215. Bit 15 of P1+1 acts as a sign bit; the number is negative if bit 15 is ON, positive if it is OFF.
Page 419 Limitations In the CPM1/CPM1A PCs, P must be 000 and C must be 000 to 002. In CPM2A/CPM2C PCs, P must be 000, 010, 100, 101, 102, or 103 and C must be 000 to 003. D and D+1 must be in the same data area.
Page 420 8-digit BCD value in D and D+1. (The leftmost 4 digits are written to D+1.) The PV can be F838 8608 to 0838 8607 in differential phase mode, pulse + di- rection input mode, or up/down input mode. (The hexadecimal “F” in the first digit acts as a minus sign.)
Page 421 Pulse output 1 acceleration (0: Constant; 1: Accelerating or decelerating) Read Range Comparison If C is 002, PRV(62) reads the results of the comparison of the PV to the 8 ranges Results (C=002) defined by CTBL(63) and writes this data to D. Bits 00 through 07 of D contain the Comparison Result Flags for ranges 1 to 8.
Page 422: Shift Instructions
St and E, i.e., if I is ON, a 1 is shifted into the regis- ter; if I is OFF, a 0 is shifted in. When I is shifted into the register, all bits previously in the register are shifted to the left and the leftmost bit of the register is lost.
Page 423 E: End word IR, SR, AR, DM, HR, LR Limitations St and E must be in the same data area, and E must be greater than or equal to DM 6144 to DM 6655 cannot be used for St or E. Description When the execution condition is OFF, WSFT(16) is not executed.
Page 424 When the execution condition is OFF, ASL(25) is not executed. When the execu- tion condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the status of bit 15 into CY.
Page 425 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 Precautions Use STC(41) to set the status of CY or CLC(41) to clear the status of CY before doing a rotate operation to ensure that CY contains the proper status before executing ROL(27).
Page 426 IR, SR, AR, DM, HR, LR Limitations St and E must be in the same data area, and E must be less than or equal to St. DM 6144 to DM 6655 cannot be used for St or E. Description When the execution condition is OFF, SRD(75) is not executed.
Page 427 IR, SR, AR, DM, HR, LR Limitations St and E must be in the same data area and St must be less than or equal to E. DM 6144 to DM 6655 cannot be used for C, St, or E.
Page 428 SRM1(-V2) if desired. Limitations St and E must be in the same data area, and E must be greater than or equal to DM 6144 to DM 6655 cannot be used for St or E.
Page 429: Data Movement Instructions
7-17 Control Word Bits 00 through 12 of C are not used. Bit 13 is the shift direction: turn bit 13 ON to shift down (toward lower addressed words) and OFF to shift up (toward higher addressed words). Bit 14 is the Shift Enable Bit: turn bit 14 ON to enable shift register operation according to bit 13 and OFF to disable the register.
Page 430 Bit status not changed. Precautions TC numbers cannot be designated as D to change the PV of the timer or counter. You can, however, easily change the PV of a timer or a counter by using BSET(71). Indirectly addressed DM word is non-existent. (Content of *DM word is Flags not BCD, or the DM area boundary has been exceeded.)
Page 431 D: Starting destination word IR, SR, AR, DM, HR, TC, LR Limitations S and S+N must be in the same data area, as must D and D+N. DM 6144 to DM 6655 cannot be used for D. Description When the execution condition is OFF, XFER(70) is not executed. When the execution condition is ON, XFER(70) copies the contents of S, S+1, ..., S+N to...
Page 432 IR, SR, AR, DM, HR, TC, LR Limitations St must be less than or equal to E, and St and E must be in the same data area. DM 6144 to DM 6655 cannot be used for St or E.
Page 433 DM 6144 and DM 6655. 2. IR 000 to IR 019 or IR 000 to IR 049 is treated as a different memory area from IR 200 to IR 255 for the source data area. The entire source data area must be within one or the other of these areas.
Page 434 Example The following example shows how to use DIST(80) to copy #00FF to HR 10 + Of. The content of LR 10 is #3005, so #00FF is copied to HR 15 (HR 10 + 5) when IR 00000 is ON.
Page 435 1. SBs and SBs+Of must be in the same data area. 2. IR 000 to IR 019 or IR 000 to IR 049 is treated as a different memory area from IR 200 to IR 255 for the source data area. The entire source data area must be within one or the other of these areas.
Page 436 When bits 12 to 15 of C=8, COLL(81) can be used for an LIFO stack operation. The other 3 digits of C specify the number of words in the stack (000 to 999). The content of SBs is the stack pointer.
Page 437 Section 7-17 When IR 00000 goes from OFF to ON, COLL(81) copies the content of DM 0005 (DM 0000 + 5) to IR 001. The content of the stack pointer (DM 0000) is then de- cremented by one. 00000 Address Instruction...
Page 438 ON, MOVB(82) copies the specified bit of S to the speci- fied bit in D. The bits in S and D are specified by Bi. The rightmost two digits of Bi designate the source bit; the leftmost two bits designate the destination bit.
Page 439: Data Control Instructions
R. The results is rounded off to the nearest integer. If the results is less than 0000, then 0000 is written to R, and if the result is greater than 9999, then 9999 is written to R.
Page 440 ) and (B Value after conversion (BCD) Value before conversion (Hexadecimal) The results can be calculated by first converting all values to BCD and then using the following formula. Results = B – [(B – A )/(B – A – S)] Flags The value in P1+1 equals that in P1+3.
Page 441 If the result is negative, then CY is set to 1. If the result is less than –9999, then –9999 is written to R. If the result is greater than 9999, then 9999 is written to R.
Page 442 When 05000 is turned ON in the following example, the signed binary source data in 200 (#FFE2) is converted to BCD according to the parameters in DM 0000 to DM 0002. The result (#0018) is then written to LR 00 and CY is turned ON because the result is negative.
Page 443 The content of S can be 0000 to 9999, but S will be treated as a negative value if CY=1, so the effective range of S is actually –9999 to 9999. Be sure to set the desired sign in CY using STC(40) or CLC(41).
Page 444 ON, the BCD source data in LR 02 is converted to signed binary accord- ing to the parameters in DM 0000 to DM 0004. The result is then written to DM 0100. (In the second conversion, the signed binary equivalent of –1035 is less than the lower limit specified in DM 0004, so the lower limit is written to DM 0100.)
Page 445 Parameter name Function/Setting range 00 to 15 Set value (SV). This is the target value for PID control. It can be set to any binary number with the number of bits set by the input range parameter. P1+1 00 to 15...
Page 446 (60 ms) PID CONTROL Action Execution Condition OFF All data that has been set is retained. When the execution condition is OFF, the manipulated variable can be written to the output word (OW) to achieve manual control. Rising Edge of the Execution Condition The work area is initialized based on the PID parameters that have been set and the PID control action is begin.
Page 447 (the difference between from SV and PV) and gradually decreased until the SV and PV match (i.e., until the deviation is 0), at which time the MV will be 0% (i.e., the minimum value). The MV will also be 0% when the PV is larger than the SV.
Page 448 (de- rivative coefficient) caused by the deviation. The strength of the derivative action is indicated by the derivative time, which is the time required for the manipulated variable of the derivative action to reach the same level as the manipulated variable of the proportional action with re- spect to the step deviation, as shown in the following illustration.
Page 449 The general relationship between PID parameters and control status is shown below. When it is not a problem if a certain amount of time is required for stabilization (settlement time), but it is important not to cause overshooting, then enlarge the proportional band.
Page 450: Comparison Instructions
Cp2: Second compare word IR, SR, AR, DM, HR, TC, LR, # Limitations When comparing a value to the PV of a timer or counter, the value must be in BCD. Description When the execution condition is OFF, CMP(20) is not executed. When the execution condition is ON, CMP(20) compares Cp1 and Cp2 and outputs the result to the GR, EQ, and LE flags in the SR area.
Page 451 R is set, e.g., if the CD equals the content of TB, bit 00 is turned ON, if it equals that of TB+1, bit 01 is turned ON, etc. The rest of the bits in R will be turned OFF.
Page 452 SRM1(-V2) if desired. Limitations Each lower limit word in the comparison block must be less than or equal to the upper limit. DM 6144 to DM 6655 cannot be used for R.
Page 453 If CD is found to be within any of these ranges (inclusive of the upper and lower limits), the corresponding bit in R is set. The comparisons that are made and the corresponding bit in R that is set for each true comparison are shown below.
Page 454 When the execution condition is OFF, CMPL(60) is not executed. When the execution condition is ON, CMPL(60) joins the 4-digit hexadecimal content of Cp1+1 with that of Cp1, and that of Cp2+1 with that of Cp2 to create two 8-digit hexadecimal numbers, Cp+1,Cp1 and Cp2+1,Cp2. The two 8-digit numbers are then compared and the result is output to the GR, EQ, and LE flags in the SR area.
Page 455 20000 is turned ON; if the two contents are equal, 20001 is turned ON; if content of HR 10, HR 09 is less than that of DM 0001, DM 0000, then 20002 is turned ON. In some applications, only one of the three OUTs would be necessary, making the use of TR 0 unnecessary.
Page 456 Precautions Placing other instructions between ZCP(––) and the operation which accesses the EQ, LE, and GR flags may change the status of these flags. Be sure to ac- cess them before the desired status is changed. Indirectly addressed DM word is non-existent. (Content of *DM word is Flags not BCD, or the DM area boundary has been exceeded.)
Page 457: Conversion Instructions
ON, ZCPL(––) compares the 8-digit value in CD, CD+1 to the range defined by lower limit LL+1,LL and upper limit UL+1,UL and outputs the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is shown in the following table.
Page 458 DM 6144 to DM 6655 cannot be used for R. Description BCD(24) converts the binary (hexadecimal) content of S into the numerically equivalent BCD bits, and outputs the BCD bits to R. Only the content of R is changed; the content of S is left unchanged. Binary...
Page 459 R and R+1 remain unchanged. DM 6144 to DM 6655 cannot be used for R. Description BCDL(59) converts the 32-bit binary content of S and S+1 into eight digits of BCD data, and outputs the converted data to R and R+1. S + 1...
Page 460 ON, MLPX(76) converts up to four, four-bit hexadecimal digits from S into decimal values from 0 to 15, each of which is used to indicate a bit position. The bit whose number corresponds to each converted value is then turned ON in a result word.
Page 461 BCD or the DM area boundary has been exceeded.) Example The following program converts digits 1 to 3 of data from DM 0020 to bit positions and turns ON the corresponding bits in three consecutive words starting with HR 10.
Page 462 S, encodes it into single-digit hexadecimal value corresponding to the bit number of the highest ON bit number, then transfers the hexadecimal value to the specified digit in R. The digits to receive the results are specified in Di, which also specifies the number of digits to be encoded.
Page 463 When 00000 is ON, the following diagram encodes IR words 200 and 201 to the first two digits of HR 10 and then encodes LR 10 and 11 to the last two digits of HR 10. Although the status of each source word bit is not shown, it is assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word.
Page 464 Any or all of the digits in S may be converted in sequence from the designated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are desig- nated in Di.
Page 465 Conversion Instructions Section 7-20 Some example Di values and the 4-bit binary to 7-segment display conversions that they produce are shown below. Di: 0011 Di: 0030 S digits S digits 1st half 1st half 2nd half 2nd half 1st half...
Page 466 7-20 Example The following example shows the data to produce an 8. The lower case letters show which bits correspond to which segments of the 7-segment display. The table underneath shows the original data and converted code for all hexadeci- mal digits.
Page 467 Any or all of the digits in S may be converted in order from the designated first digit. The first digit, the number of digits to be converted, and the half of D to re- ceive the first ASCII code (rightmost or leftmost 8 bits) are designated in Di. If multiple digits are designated, they will be placed in order starting from the des- ignated half of D, each requiring two digits.
Page 468 Parity The leftmost bit of each ASCII character (2 digits) can be automatically adjusted for either even or odd parity. If no parity is designated, the leftmost bit will always be zero. When even parity is designated, the leftmost bit will be adjusted so that the total number of ON bits is even, e.g., when adjusted for even parity, ASCII “31”...
Page 469 All source words must be in the same data area. Bytes in the source words must contain the ASCII code equivalent of hexadeci- mal values, i.e., 30 to 39 (0 to 9) or 41 to 46 (A to F). DM 6144 to DM 6655 cannot be used for D.
Page 470 ASCII character should be adjusted so that there is an odd or even number of ON bits. If the parity of the ASCII code in S does not agree with the parity specified in Di, the ER Flag (SR 25503) will be turned ON and the instruction will not be...
Page 471 This instruction is available in the CPM2A/CPM2C only. S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be in the proper hours/min- utes/seconds format.
Page 472 This instruction is available in the CPM2A/CPM2C only. S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and S+1 must be BCD and must be between 0 and 35,999,999 seconds.
Page 473 S from 0000 and outputting the result to R; it will calculate the absolute value of negative signed binary data. If the content of S is 0000, the content of R will also be 0000 after execution and EQ (SR 25506) will be turned on.
Page 474 Conversion Instructions Section 7-20 Example The following example shows how to use NEG(––) to find the 2’s complement of the content of DM 0005 and output the result to IR 105. 00100 Address Instruction Operands NEG(––) 00000 00100 DM 0005 00001 NEG(––)
Page 475: Bcd Calculation Instructions
When the execution condition is OFF, ADD(30) is not executed. When the execution condition is ON, ADD(30) adds the contents of Au, Ad, and CY, and places the result in R. CY will be set if the result is greater than 9999. Au + Ad + CY Flags Au and/or Ad is not BCD.
Page 476 ON, SUB(31) subtracts the contents of Su and CY from Mi, and places the result in R. If the result is negative, CY is set and the 10’s com- plement of the actual result is placed in R. To convert the 10’s complement to the true result, subtract the content of R from zero (see example below).
Page 477 When 00002 is ON, the following ladder program clears CY, subtracts the con- tents of DM 0100 and CY from the content of 201 and places the result in HR 10. If CY is set by executing SUB(31), the result in HR 10 is subtracted from zero (note that CLC(41) is again required to obtain an accurate result), the result is placed back in HR 10, and HR 1100 is turned ON to indicate a negative result.
Page 478 HR 10 2423 (0000 + (10000 – 7577)) (negative result) In the above case, the program would turn ON HR 1100 to indicate that the value held in HR 10 is negative. 7-21-5 BCD MULTIPLY – MUL(32) Operand Data Areas...
Page 479 IR, SR, AR, DM, HR, TC, LR, # R: First result word (BCD) IR, SR, AR, DM, HR, LR Limitations R and R+1 must be in the same data area. DM 6144 to DM 6655 cannot be used for R.
Page 480 When the execution condition is OFF, DIV(33) is not executed and the program moves to the next instruction. When the execution condition is ON, Dd is divided by Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1.
Page 481 ON, ADDL(54) adds the contents of CY to the 8-digit val- ue in Au and Au+1 to the 8-digit value in Ad and Ad+1, and places the result in R and R+1. CY will be set if the result is greater than 99999999.
Page 482 ON, SUBL(55) subtracts CY and the 8-digit contents of Su and Su+1 from the 8-digit value in Mi and Mi+1, and places the result in R and R+1. If the result is negative, CY is set and the 10’s complement of the actual result is placed in R.
Page 483 The following example works much like that for single-word subtraction. In this example, however, BSET(71) is required to clear the content of DM 0000 and DM 0001 so that a negative result can be subtracted from 0 (inputting an 8-digit constant is not possible).
Page 484 ON, DIVL(57) the eight-digit content of Dd and D+1 is di- vided by the content of Dr and Dr+1 and the result is placed in R to R+3: the quo- tient in R and R+1, the remainder in R+2 and R+3.
Page 485: Binary Calculation Instructions
When the execution condition is OFF, ADB(50) is not executed. When the execution condition is ON, ADB(50) adds the contents of Au, Ad, and CY, and places the result in R. CY will be set if the result is greater than FFFF. Au + Ad + CY ADB(50) can also be used to add signed binary data.
Page 486 HR 11 = R+1 00001 In the case below, A6E2 + 80C5 = 127A7. The result is a 5-digit number, so CY (SR 25504) = 1, and the content of R + 1 becomes #0001. Au: IR 200 Ad: DM 0100...
Page 487 ON, SBB(51) subtracts the contents of Su and CY from Mi and places the result in R. If the result is negative, CY is set and the 2’s comple- ment of the actual result is placed in R.
Page 488 When the execution condition is OFF, DVB(53) is not executed. When the execution condition is ON, DVB(53) divides the content of Dd by the content of Dr and the result is placed in R and R+1: the quotient in R, the remainder in R+1. Quotient...
Page 489: Special Math Instructions
DM area: 1, 2, 3... 1. For an address in the DM area, the word address is written to C+1. For ex- ample, if the lowest address containing the comparison data is DM 0114, then #0114 is written in C+1.
Page 490 The address is identified differently for the DM area: 1, 2, 3... 1. For an address in the DM area, the word address is written to C+1. For ex- ample, if the address containing the maximum value is DM 0114, then #0114 is written in D+1.
Page 491 Section 7-23 If bit 14 of C is ON and more than one address contains the same maximum val- ue, the position of the lowest of the addresses will be output to D+1. The position will be output as the DM address for the DM area, but as an absolute position relative to the first word in the range for all other areas.
Page 492 Special Math Instructions Section 7-23 ue will be stored in DM 0500. The offset from the beginning of the search of the word containing the maximum value will be stored in DM 0501. 00000 Address Instruction Operands MAX(––) 00000 00000...
Page 493 IR 014, then #0100 is written in D+1. If bit 14 of C is ON and more than one address contains the same minimum val- ue, the position of the lowest of the addresses will be output to D+1. The position will be output as the DM address for the DM area, but as an absolute position relative to the first word in the range for all other areas.
Page 494 When the execution condition is OFF, AVG(––) is not executed. Each time that AVG(––) is executed, the content of S is stored in words D+2 to D+N+1. On the first execution, AVG(––) writes the content of S to D+2; on the second execution it writes the content of S to D+3, etc.
Page 495 Content of S from the N execution of AVG(––) Precautions The average value is calculated in binary. Be sure that the content of S is in binary. N must be BCD from #0001 to #0064. If the content of N #0065, AVG(––) will...
Page 496 Addition Units Words will be added if bit 13 is OFF and bytes will be added if bit 13 is ON. If bytes are specified, the range can begin with the leftmost or rightmost byte of .
Page 497: Logic Instructions
The bytes will be added in this order when bit 12 is ON: 2+3+4..Data Type Data within the range is treated as unsigned binary when bit 14 of C is ON and bit 15 is OFF, and it is treated as signed binary when both bits 14 and 15 are ON.
Page 498 Logic Instructions Section 7-24 Precautions The complement of Wd will be calculated every cycle if the undifferentiated form of COM(29) is used. Use the differentiated form (@COM(29)) or combine COM(29) with DIFU(13) or DIFD(14) to calculate the complement just once. Example...
Page 499 DM 6144 to DM 6655 cannot be used for R. Description When the execution condition is OFF, ORW(35) is not executed. When the execution condition is ON, ORW(35) logically OR’s the contents of I1 and I2 bit- by-bit and places the result in R. Example Indirectly addressed DM word is non-existent.
Page 500 7-24 Description When the execution condition is OFF, XORW(36) is not executed. When the execution condition is ON, XORW(36) exclusively OR’s the contents of I1 and I2 bit-by-bit and places the result in R. Example Indirectly addressed DM word is non-existent. (Content of *DM word is Flags not BCD, or the DM area boundary has been exceeded.)
Page 501: Increment/Decrement Instructions
ON, INC(38) increments Wd, without affecting Carry (CY). Precautions The content of Wd will be incremented every cycle if the undifferentiated form of INC(38) is used. Use the differentiated form (@INC(38)) or combine INC(38) with DIFU(13) or DIFD(14) to increment Wd just once.
Page 502: Subroutine Instructions
When all the subroutine instructions have been executed, control returns to the main program to the point just after the point from which the subroutine was entered (unless otherwise specified in the subroutine).
Page 503 (i.e., RET(93) has been reached), program execution returns to the original subroutine which is then completed before re- turning to the main program. Nesting is possible to up to sixteen levels. A sub- routine cannot call itself (e.g., SBS(91) 000 cannot be programmed within the subroutine defined with SBN(92) 000).
Page 504 There are 4 input words (SR 232 to SR 235) and 4 output words (SR 236 to SR 239), allocated to MCRO(99). These 8 words are used in the subroutine and take their contents from I1 to I1+3 and O1 to O1+3 when the subroutine is executed.
Page 505: Pulse Output Instructions
Note Refer to page 157 for more details on MCRO(99). Example In this example, the contents of DM 0010 through DM 0013 are copied to SR 232 through SR 235, and then subroutine 10 is called and executed. When the sub- routine is completed, the contents of SR 236 through SR 239 are copied to out- put words DM 0020 to DM 0023.
Page 506 N+1 and N contain the 8-digit BCD number of output pulses setting for indepen- dent mode pulse outputs. The number of output pulses can be –16,777,215 to 16,777,215. Bit 15 of N+1 acts as a sign bit; the number is negative if bit 15 is ON, positive if it is OFF.
Page 507 Pulse Output Instructions Section 7-27 ue of the number of movement pulses will be used. (For example, if the number of movement pulses is –500, a value of 500 will be used.) Flags A data area boundary is exceeded. Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.)
Page 508 Operation in independent mode and continuous mode is described below. Target Frequency (F) The 4-digit BCD value of F sets the pulse frequency in units of 10 Hz, as shown below. Setting F to 0000 will stop the pulse output from the specified output bit.
Page 509 BCD, or the DM area boundary has been exceeded.) P is not 000 or 010, M is not 000 or 001, or F is not 0000 to 1000. SPED(64) is executed in an interrupt subroutine while a pulse I/O or...
Page 510 The content of C+2 determines the deceleration rate. During deceleration, the output frequency is decreased by the amount set in C+2 every 10 ms. C must be BCD from 0001 to 1000 (10 Hz to 10 kHz). General Operation Two output bits are required for pulse outputs controlled by ACC(––).
Page 511 Section 7-27 Operation in Independent In independent mode, just the number of output pulses set by PULS(65) will be Mode output. The number of output pulses must be specified by executing PULS(65) before executing ACC(––). (Pulses won’t be output if the number of output pulses has not been specified in advance.)
Page 512 BCD, or the DM area boundary has been exceeded.) P is not 000. M is not 000, 002, or 010 to 013. (The mode specifier is read only when starting the pulse output.) ACC(––) is executed for a bit from which pulses are already being out- put by PWM(––) or SPED(64).
Page 513 7-27 Limitations This instruction is available in the CPM2A/CPM2C only. P must be 000 or 010, F must be BCD between 0001 and 9999, and D must be BCD between 0001 and 0100. Description PWM(––) is used to output pulses with the specified duty ratio from the specified output bit.
Page 514 The 4-digit BCD value of C sets the scaling factor by which the input frequency is multiplied. The scaling factor can be set between 0001 and 1000 (1 to 1,000%). PC Setup Settings and The counter input mode for inputs 00000 and 00001 is set in bits 00 to 03 of General Operation DM 6642.
Page 515: Special Instructions
Indirectly addressed DM word is non-existent. (Content of *DM word is not BCD, or the DM area boundary has been exceeded.) P1 is not 000, P2 is not 000 or 010, or C is not BCD between 0001 and 1000.
Page 516 Up to three messages can be buffered in memory. Once stored in the buffer, they Priority are displayed on a first in, first out basis. Since it is possible that more than three MSG(46)s may be executed within a single cycle, there is a priority scheme, based on the area where the messages are stored, for the selection of those messages to be buffered.
Page 517 SB and SB+(N–1) and places the result in R. Flags N is not BCD, or N is 0; SB and SB+(N–1) are not in the same area. A DM address is used for SB, but SB through SB+(N–1) are not all in read/write DM.
Page 518 12 is ON. MSB LSB When bit 12 is OFF the bytes will be ORed in this order: 1, 2, 3, 4, ..When bit 12 is ON the bytes will be ORed in this order: 2, 3, 4, 5, ..
Page 519: Interrupt Control Instructions
0008 DM 0010 0000 0010 DM 0000 0001 calculation DM 0001 0002 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 DM 0002 0003 DM 0003 0004 DM 0004 0005 ASCII code conversion...
Page 520 Inputs (C1=000) Masked inputs are recorded, but ignored. When an input is masked, the interrupt program for it will be run as soon as the bit is unmasked (unless it is cleared be- forehand by executing INT(89) with C1=001). Set the corresponding bit in C2 to 0 or 1 to unmask or mask an interrupt input.
Page 521 INT(89) with C1=003 or C1=004. The counter PV will be reset to the SV if INT(89) is executed while the counter is operating, so the interrupt will never be generated if INT(89) is executed every cycle.
Page 522 Limitations C1 must be 000, 003, 006. or 010. If C1 is 000 or 003, C3 represents a BCD subroutine number up to 0049. If C1 is 006, constants cannot be used for C2 or C3. If C1 is 010, both C2 and C3 must be set to 000.
Page 523: Communications Instructions
If C2 is a constant, it specifies the SV of the decrementing counter in BCD. The setting range is 0000 to 9999 (0 to 9.999 ms). (The timing units are fixed at 1 ms.) C3 specifies subroutine number: 0000 to 0049.
Page 524 0: RS-232C port. 1: Peripheral port. The order in which data is written to memory depends on the value of digit 0 of C. Eight bytes of data 12345678... will be written in the following manner: Digit 0 = 0...
Page 525 PC Setup, etc. Host Link Mode N must be BCD from #0000 to #0061 (i.e., up to 122 bytes of ASCII). The value of the control word determines the port from which data will be output, as shown below.
Page 526 MSB LSB When digit 0 of C is 0, the bytes of source data shown above will be transmitted in this order: 12345678... When digit 0 of C is 1, the bytes of source data shown above will be transmitted in this order: 21436587...
Page 527 RS-232C Setup for the built-in RS-232C port (DM 6645 to DM 6649) only. If S is a word address, the contents of S through S+4 are copied to DM 6645 to DM 6649. If S is input as the constant #0000, the settings for the built-in RS-232C port are returned to their default values.
Page 528 Communications Instructions Section 7-30 Application Example This example shows a program that transfers the contents of DM 0100 through DM 0104 to the PC Setup area for the built-in RS-232C port (DM 6645 through DM 6649). 00000 Address Instruction Operands @STUP(––)
Page 529: Pc Operations And Processing Time
This section explains the internal processing of the CPM1, CPM1A, CPM2A, CPM2C, and SRM1(-V2), as well as the time required for processing and execution. Refer to this section to gain an understanding of the precise timing of PC operation. CPM1/CPM1A Cycle Time and I/O Response Time .
Page 530: Cpm1/Cpm1A Cycle Time And I/O Response Time
CPM1/CPM1A Cycle Time and I/O Response Time Section CPM1/CPM1A Cycle Time and I/O Response Time 8-1-1 The CPM1/CPM1A Cycle The overall flow of CPM1/CPM1A operation is as shown in the following flow- chart. Power application Initialization processes Initialization Check hardware and Program Memory.
Page 531: Cpm1/Cpm1A Cycle Time
Cycle time Operation conditions 10 ms or longer TIMH(15) may be inaccurate when TC 004 through TC 127 are used (operation will be normal for TC 000 through TC 003). 20 ms or longer Programming using the 0.02-second Clock Bit (SR 25401) may be inaccurate.
Page 532: I/O Response Time
The I/O response time is the time it takes after an input signal has been received (i.e., after an input bit has turned ON) for the PC to check and process the in- formation and to output a control signal (i.e., to output the result of the proces- sing to an output bit).
Page 533: One-To-One Pc Link I/O Response Time
(LR) The following conditions are taken as examples for calculating the I/O response times. In CPM1/CPM1A PCs, LR area words LR 00 to LR 15 are used in 1:1 data links and the transmission time is fixed at 12 ms.
Page 534 Slave #1 Slave #2 Output OFF Slave #3 response time Slave Output point Maximum I/O response time = 8 + 10 x 2 + 12 x 3 + 15 x 3 + 10 = 119 (ms)
Page 535: Interrupt Processing Time
Item Contents Time Interrupt ON delay This is the delay time from the time the interrupt input bit turns ON until the 100 s time that the interrupt is executed. This is unrelated to other interrupts. Wait for completion of This is the time during which interrupts are waiting until processing has See below.
Page 536: Cpm1/Cpm1A Instruction Execution Times
Section In addition to the response time shown above, the time required for executing the interrupt processing routine itself and a return time of 30 s must also be ac- counted for when returning to the process that was interrupted.
Page 537 CPM1/CPM1A Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) TIMH Reset 19.0 Regular execution, constant for SV 25.7 28.4 15.8 20.2 Interrupt execution, constant for SV Regular execution, :DM for SV 41.2...
Page 538 CPM1/CPM1A Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) 27.1 Constant V word word 28.7 Word V word word :DM V :DM 70.7 XORW 27.1...
Page 539 Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) CTBL 106.3 Target table with 1 target in words and start Target table with 1 target in :DM and start 120.3 775.5 Target table with 16 targets in words and start Target table with 16 targets in :DM and start 799.5...
Page 540 When decoding word to word When decoding :DM to :DM 96.3 DIST 39.1 When setting a constant to a word + a word 40.9 When setting a word to a word + a word When setting :DM to :DM +:DM 84.7 63.4...
Page 541: Cpm2A/Cpm2C Cycle Time And I/O Response Time
Cycle time Operation conditions 1 ms or longer TMHH(––) may be inaccurate when TC 000 through TC 003 or TC 008 through TC 255 are used (operation will be normal for TC 004 through TC 007). 10 ms or longer TIMH(15) may be inaccurate when TC 004 through TC 255 are used (operation will be normal for TC 000 through TC 003).
Page 542: I/O Response Time
The I/O response time is the time it takes after an input signal has been received (i.e., after an input bit has turned ON) for the PC to check and process the in- formation and to output a control signal (i.e., to output the result of the proces- sing to an output bit).
Page 543: One-To-One Pc Link I/O Response Time
CPM2A/CPM2C Cycle Time and I/O Response Time Section Minimum I/O Response Time The CPM2A/CPM2C responds most quickly when it receives an input signal just prior to I/O refreshing, as shown in the illustration below. Input point Input ON delay (10 ms)
Page 544 Output point Min. I/O response time = 10+10+12+15+15 = 62 ms Maximum I/O Response Time The CPM2A/CPM2C takes the longest to respond under the following circum- stances: 1, 2, 3... 1. The CPM2A/CPM2C receives an input signal just after the input refresh phase of the cycle.
Page 545: Interrupt Processing Time
Contents Time Interrupt ON delay This is the delay time from the time the interrupt input bit turns ON until the 100 s time that the interrupt is executed. This delay does not affect other interrupts. Wait for completion of When a process that disables (masks) the interrupt is being executed, this is See below.
Page 546: Cpm2A/Cpm2C Instruction Execution Times
Section In addition to the response time shown above, the time required for executing the interrupt processing routine itself and a return time of 30 s must also be ac- counted for when returning to the process that was interrupted.
Page 547 CPM2A/CPM2C Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) TIMH Reset Regular execution, constant for SV 13.0 12.6 Interrupt execution, constant for SV 14.4 14.0...
Page 548 CPM2A/CPM2C Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) 12.3 Constant V constant word 13.8 Word V word word :DM V :DM 35.4 XORW 12.3...
Page 549 CPM2A/CPM2C Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) 68.8 Starting high-speed counter comparison 12.0 Stopping high-speed counter comparison 43.3 Specifying a constant when changing high-...
Page 550 CPM2A/CPM2C Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) CTBL 186.0 Registering a target value comparison table and starting comparison in incrementing/decrement- ing pulse input mode via word 807.5...
Page 551 When decoding word to word When decoding :DM to :DM 48.3 DIST 18.7 When setting a constant to a word + a word 20.2 When setting a word to a word + a word When setting :DM to :DM +:DM 43.1 31.0...
Page 552 Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) COLL 21.5 When setting a constant + a word to a word 21.9 When setting a word + a word to a word When setting :DM + :DM to :DM 42.5 31.5...
Page 553 CPM2A/CPM2C Cycle Time and I/O Response Time Section Expansion Instructions without Default Function Codes Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) 66.5 When specifying a word in independent mode and CW/CCW mode When specifying :DM in independent mode 92.1...
Page 554 13.6 25.1 24.7 Comparing a constant to a constant range and output to word 11.8 Comparing a word to a word range and output to word Comparing :DM to :DM and output to :DM 33.4 ZCPL 19.5 Comparing a word to a word range Comparing :DM to :DM 45.2...
Page 555: Srm1(-V2) Cycle Time And I/O Response Time
Note 1. The cycle time can be read using Programming Devices. 2. Cycle time maximum and current cycle time are stored in AR 14 and AR 15. 3. Change to processing will cause cycle times to change therefore the calcu-...
Page 556: Srm1(-V2) Cycle Time
CompoBus/S communications are completed. The minimum cycle time therefore is the the CompoBus/S communications re- sponse time plus the program execution time plus the input refresh time plus the output refresh time. The CompoBus/S communications response time depends on the “maximum number of nodes” and “communications mode” settings, as follows: Max.
Page 557 Cycle time Operation conditions 10 ms or longer TIMH(15) may be inaccurate when TC 004 through TC 127 are used (operation will be normal for TC 000 through TC 003). 20 ms or longer Programming using the 0.02-second Clock Bit (SR 25401) may be inaccurate.
Page 558: I/O Response Time
The I/O response time is the time it takes after an input signal has been received (i.e., after an input bit has turned ON) for the PC to check and process the in- formation and to output a control signal (i.e., to output the result of the proces- sing to an output bit).
Page 559: One-To-One Pc Link I/O Response Time
8-3-4 One-to-one PC Link I/O Response Time When two SRM1s are linked in a 1:1 PC Link, the I/O response time is the time required for an input executed at one of the SRM1s to be output to the other SRM1 by means of 1:1 PC Link communications.
Page 560: Interrupt Processing Time
This is the time it takes to change processing to an interrupt. 15 s processing Return This is the time it takes, from execution of RET(93), to return to the proces- 15 s sing that was interrupted. Mask Processing Interrupts are masked during processing of the operations described below. Un- til the processing is completed, any interrupts will remain masked for the indi- cated times.
Page 561: Srm1(-V2) Instruction Execution Times
Section Online editing: Interrupts will be masked for a maximum of 600 ms (i.e.: editing DM 6144 to DM 6655) when online editing is executed during operation. In addition, the system processing may have to wait for a maximum of 170 s during this processing.
Page 562 SRM1(-V2) Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) DIFD Shift TIMH 10.3 Reset Regular execution, constant for SV 14.1 13.9 10.9 Interrupt execution, constant for SV 15.6...
Page 563 SRM1(-V2) Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) ANDW 14.3 Constant word word 15.2 Word word word 37.3 14.3 Constant V word word 15.2...
Page 564 When decoding word to word When decoding :DM to :DM 49.9 DIST 21.3 When setting a constant to a word + a word 21.9 When setting a word to a word + a word When setting :DM to :DM +:DM 45.7 34.3...
Page 565 Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) COLL 21.4 When setting a constant + a word to a word 21.8 When setting a word + a word to a word When setting :DM + :DM to :DM 44.9 34.0...
Page 566 SRM1(-V2) Cycle Time and I/O Response Time Section Code Mnemonic ON execution Conditions (Top: min.; bottom: max.) OFF execution time ( s) time ( s) 45.0 Comparing a word to a constant range 46.5 Comparing a word to a word range Comparing :DM to :DM 69.0...
Page 567: Troubleshooting
SECTION 9 Troubleshooting This section describes how to diagnose and correct the hardware and software errors that can occur during PC operation. Introduction .............
Page 568: Introduction
The error code is also contained in SR 25300 to SR 25307. For the most recent errors, both the type of error and time of occurrence will be recorded in the PC’s error log area. Details are provided starting on page 555.
Page 569: Programming Errors
Check level 0 checks for type A, B, and C errors; check level 1, for type A and B errors; and check level 2, for type A errors only.
Page 570: User-Defined Errors
69, 87, 88, and 89) are not subject to program checks. Program checks also do not cover DM 1024 to DM 6143 for PCs that do not support this part of the DM area. Data will not be written even if these areas are specified and data read from these areas will always be “0000.”...
Page 571: Operating Errors
An error has been detected in the PC Setup. Check flags AR 1300 to AR 1302, and correct as directed. AR 1300 ON: An incorrect setting was detected in the PC Setup (DM 6600 to DM 6614) when power was turned on.
Page 572 AR 1310 ON: A checksum error has occurred in read-only DM (DM 6144 to DM 6599). Check and correct the settings in the read-only DM area. AR 1311 ON: A checksum error has occurred in the PC Setup. Initialize all of the PC Setup and re-input.
Page 573: Error Log
DM1020 DM1021 Error Log Storage Methods The error log storage method is set in the PC Setup (DM 6655). Set any of the following methods. 1, 2, 3... 1. You can store the most recent 10 error log records and discard older re- cords.
Page 574 Error Log Section Note An error record with an error code of 00 will be stored in the error log for power interruptions. Error Log Storage Methods The error log storage method is set in the PC Setup (DM 6655). Set any of the following methods.
Page 575: Host Link Errors
Section 3. You can disable the log so that no records are stored. The default setting is the first method. Refer to Error Log Settings on page 21 for details on the PC Setup for the error log. Clearing the Error Log To clear the entire error log, turn ON SR 25214 from a Programming Device.
Page 576: A Programming Instructions
A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND, OR, NOT) or by using function codes. To input an instruction with its function code, press FUN, the function code, and then WRITE. Refer to the pages listed programming and instruction details.
Page 577 Converts binary data in source word into BCD, and outputs converted data to result word. (@)ASL ARITHMETIC SHIFT Shifts each bit in single word of data one bit to left, with CY. LEFT (@)ASR ARITHMETIC SHIFT Shifts each bit in single word of data one bit to right, with CY.
Page 578 (four bits). (@)MLPX 4-TO-16 DECODER Converts up to four hexadecimal digits in source word into decimal values from 0 to 15 and turns ON, in result word(s), bit(s) whose position corresponds to converted value. (@)DMPX 16-TO-4 ENCODER Determines position of highest ON bit in source word(s) and turns ON corresponding bit(s) in result word.
Page 579 Appendix A Expansion Instructions The following table shows the instructions that can be treated as expansion instructions in the CPM2A, CPM2C, and SRM1(-V2) PCs. The default function codes are given for instructions that have codes assigned by default. Code Mnemonic...
Page 580 A high-speed, decrementing ON-delay timer that CPM2A/ TIMER times in 1-ms units CPM2C AREA RANGE COMPARE Compares a word to a range defined by lower and upper limits and outputs the result to the (But, Ver- GR, EQ, and LE flags. sion 2 only...
Page 581: B Error And Arithmetic Flag Operation
CY indicates arithmetic or data shift results. GT indicates that a compared value is larger than some standard, LT that it is smaller, and EQ, that it is the same. EQ also indicates a result of zero for arithmetic operations.
Page 582 Error and Arithmetic Flag Operation Appendix B Instructions 25503 (ER) 25504 (CY) 25505 (GR) 25506 (EQ) 25507 (LE) 25402 (N) Page MUL(32) Unaffected Unaffected Unaffected Unaffected DIV(33) ANDW(34) ORW(35) XORW(36) XNRW(37) INC(38) Unaffected DEC(39) STC(40) Unaffected Unaffected Unaffected Unaffected Unaffected...
Page 583 Unaffected Unaffected Unaffected HEX(––) AVG(––) PID(––) ZCP(––) Unaffected Note *Depending on the results, NEG(––) may also affect the status of the underflow flag (SR 25405). Expansion Instructions (CPM2A/CPM2C Only) Instructions 25503 (ER) 25504 (CY) 25505 (GR) 25506 (EQ) 25507 (LE) Page PWM(––)
Page 584: C Memory Areas
Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, AR area, Counter area, and read/write DM area are backed up by a capaci- tor.
Page 585 00 to 15 Input Interrupt 0 Counter Mode SV SV when input interrupt 0 is used in counter mode (4 digits hexadecimal). (Can be used as work bits when input interrupt 0 is not used in counter mode.) SR 241...
Page 586 ON: The status of bits that are forced set/reset are maintained when switch- ing between PROGRAM mode and MONITOR mode. The status of this bit can be maintained when PC power turns off by using the PC Setup. I/O Hold Bit (See note.) OFF: IR and LR bits are reset when starting or stopping operation.
Page 587 Not used. Note DM 6601 in the PC Setup can be set to maintain the previous status of the I/O Hold Bit (SR 25212) and the I/O Hold Bit (SR 25212) when power is turned OFF. If power is left OFF for longer than the backup time, however, status may be cleared.
Page 588 Not used. AR 13 Power-up PC Setup Error Flag Turns ON when there is an error in DM 6600 to DM 6614 (the part of the PC Setup area that is read at power-up). Start-up PC Setup Error Flag Turns ON when there is an error in DM 6615 to DM 6644 (the part of the PC Setup area that is read at the beginning of operation).
Page 589 2. Areas that cannot be used are cleared when the power is turned on. 3. The contents of AR 10 is backed up by the built-in capacitor. If power is left OFF for longer than the back- up time, however, the contents may be cleared. For details regarding the backup time, refer to the CPM1A or CPM1 Operation Manual.
Page 590 (In CPM2C CPU Units without a battery, these areas are backed up by a capacitor. At 25_C, the capacitor will back up memory for 10 days.) 3. When a TC number is used as a word operand, it accesses the timer or counter’s PV; when used as a bit operand, it accesses the Completion Flag.
Page 591 ON: The status of bits that are forced set/reset are maintained when switch- ing between PROGRAM mode and MONITOR mode. The PC Setup can be set to maintain the status of this bit when the PC is turned off. I/O Hold Bit (See note.) OFF: IR and LR bits are reset when starting or stopping operation.
Page 592 Not used. Note DM 6601 in the PC Setup can be set to maintain the previous status of the Forced Status Hold Bit (SR 25211) and the I/O Hold Bit (SR 25212) when power is turned OFF. Refer to 1-1-3 CPM2A/CPM2C PC...
Page 593 Memory Areas Appendix C AR Area These bits mainly serve as flags related to CPM2A/CPM2C operation. These bits retain their status even after the CPM2A/CPM2C power supply has been turned off or when operation begins or stops. Word(s) Bit(s) Function...
Page 594 Page AR 11 00 to 07 High-speed Counter Range Comparison Flags 00 ON: Counter PV is within comparison range 1 (Note 1) 01 ON: Counter PV is within comparison range 2 02 ON: Counter PV is within comparison range 3...
Page 595 Page AR 13 Power-up PC Setup Error Flag Turns ON when there is an error in DM 6600 to DM 6614 (the part of the PC Setup area that is read at power-up). Start-up PC Setup Error Flag Turns ON when there is an error in DM 6615 to DM 6644 (the part of the PC Setup area that is read at the beginning of operation).
Page 596 Note 1. The same data can be read immediately with PRV(62). 2. The time and date can be set while AR 2114 is ON. The new setting becomes effective when AR 2115 is turned ON. (AR 2114 and AR 2115 are turned OFF automatically when the new setting goes into effect.) These words will contain 0000 in CPM2C CPU Units that are not equipped with the clock function.
Page 597 Note 1. IR and LR bits that are not used for their allocated functions can be used as work bits. 2. The contents of the HR area, LR area, Counter area, and read/write DM area are backed up by a capaci- tor.
Page 598 The error code (a 2-digit number) is stored here when an error occurs. The only FAL number is stored here when FAL(06) or FALS(07) is executed. This word is reset (to 00) by executing a FAL 00 instruction or by clearing the error from a Programming Device. Not used.
Page 599 08 to 15 Not used. AR Area These bits mainly serve as flags related to SRM1 operation. These bits retain their status even after the SRM1 power supply has been turned off or when operation begins or stops. Word(s) Bit(s)
Page 600 Not used. AR 13 Power-up PC Setup Error Flag Turns ON when there is an error in DM 6600 to DM 6614 (the part of the PC Setup area that is read at power-up). Start-up PC Setup Error Flag Turns ON when there is an error in DM 6615 to DM 6644 (the part of the PC Setup area that is read at the beginning of operation).
Page 601: D I/O Assignment Sheet
Appendix D I/O Assignment Sheet Name of system Produced by Verified by Authorized by PC model Sheet No. IR_____ Unit No.: Model: IR_____ Unit No.: Model: IR_____ Unit No.: Model: IR_____ Unit No.: Model:...
Page 602: E Program Coding Sheet
Appendix E Program Coding Sheet Name of system Produced by Verified by Authorized by Chart No. Address Instruction Function Operands code...
Page 603 Program Coding Sheet Appendix E Address Instruction Function Operands code...
Page 604 Program Coding Sheet Appendix E Address Instruction Function Operands code...
Page 605: F List Of Fal Numbers
Appendix F List of FAL Numbers Name of system Produced by Verified by Authorized by PC model Chart No. FAL contents Corrective measure FAL contents Corrective measure...
Page 606 List of FAL Numbers Appendix F FAL contents Corrective measure FAL contents Corrective measure...
Page 607: G Extended Ascii
Appendix G Extended ASCII The following codes are used to output characters to the Programming Console or Data Access Console using MSG(46). Refer to pages 497 for details. Right Left digit di i digit 0, 1, 8, 9...
Page 608: Index
NT Link, CPM1/CPM1A, 228 CPM1/CPM1A, 229 types, 226 CPM2A/CPM2C, 263 wiring, 226 SRM1, 279 communications functions, 225 1:1 PC Link communications, I/O response timing Communications Switch, setting CPM1/CPM1A, 515 CPM2A, 253, 262, 266 CPM2A/CPM2C, 525 CPM2C, 254, 262, 267 SRM1, 541...
Page 609 IC, 305 error messages, programming, 497 KC, 299 errors KR, 297 communications, 554 KS, 296 MF, 295 degree of error in pulse outputs, 146 MM, 300 fatal, 554 MS, 293 general, 550 QQ, 302 non-fatal, 553 R#, 289 other, 554...
Page 610 Index CPM2A/CPM2C, 49 KEEP(11), 379 selecting, 137 in controlling bit status, 355 ladder instructions, 337 input time constants, PC Setup settings, 19 LD, 338, 376 inputs, quick-response inputs, 153 LD NOT, 338, 376 MAX(––), 472 instruction set, 559 MCRO(99), 157, 486 ACC(––), 491...
Page 611 SET and RESET, 354 SRM1, 542 using SET and RSET, 378–379 converting to mnemonic code, 336–354 interrupts display via GPC, FIT, LSS, or SSS, 335 control, 501 instructions CPM1/CPM1A combining, AND LD and OR LD, 344 counter mode, 82...
Page 612 CPM2A/CPM2C, 7 CPM2A/CPM2C, 578 SRM1(-V2), 13 SRM1, 584 peripheral port, servicing time, 18 flags and control bits CPM1/CPM1A, 569 peripheral port servicing time, PC Setup settings, 18 CPM2A/CPM2C, 575 positioning, 126 SRM1, 582 structure precautions, general, xvii CPM1/CPM1A, 308, 569...
Page 613 SRM1, 273 temperature sensor input functions, 147 RS-232C port, servicing time (CPM2A/CPM2C/SRM1), 18 Temperature Sensor Units, 147, 193 RS-232C port servicing time, PC Setup settings, 18 time RXD(47), 252, 276 reading the time, 163 setting the time, 163 timers, conditions when reset, 389, 390 TIML(––), 393...
Page 614: Revision History
Page 24: Position of notes changed. Pages 54, 55, 56, 57, 58, 71, 79, 92, 99, 106, 107, 112, 113, 115, 116, 117, 119, 133, 153, 154, 160, 174, 175, 198, 201, 213, 348, 414, 425, 428, 429: Changes to graphics.
Page 615 February 2001 Revisions and additions were made accompanying specifications changes and new products. The CPM1A-MAD11 Analog I/O Unit was added as section 3-1-2 and the CPM1A-DRT21 DeviceNet I/O Link Unit was added as section 3-4. Interrupt programming precautions were added to sections 2-1 and 2-3.

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Omron CPM1 - PROGRAMING MANUAL 02-2001 Programming Manual

Table of Contents

Precautions

Section 1 PC Setup

Section 2 Special Features

Section 3 Using Expansion Units

Section 3

Using Expansion Units

Section 4 Communications Functions

Section 5 Memory Areas

Memory Areas

Ladder-Diagram Programming

Instruction Set

Section 8

PC Operations and Processing Time

Troubleshooting

Index

Revision History

Quick Links

Chapters

Troubleshooting

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Summary of Contents for Omron CPM1 - PROGRAMING MANUAL 02-2001