Mitsubishi MELSEC-Q Series User Manual page 43

Programmable controller multiple cpu system
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OUTLINE
(5) Communication between CPU modules in the multiple CPU system
The following data transfer can be made between CPU modules in the multiple CPU
system.
(a) Data transfer between CPU modules
(b) Reading data in another CPU
(c) Control direction to the Motion CPU
(d) Writing/reading device data from the QCPU to the Motion CPU
(e) Event issue to the C Controller module or PC CPU module
POINT
The following data transfer can be made between CPU modules in the multiple
CPU system.
The QCPU can read data in another CPU with the following instruction when
necessary.
• The read instruction from another CPU shared memory
• Multiple CPU shared device (U3En\G )
The QCPU can direct control to the Motion CPU with the following instruction.
• Motion dedicated instruction
The QCPU can write/read device data to/from the Motion CPU with the following
instructions.
• Multiple CPU transmission dedicated instruction
• Multiple CPU high-speed transmission dedicated instruction
The QCPU can issue an event to the C Controller module or PC CPU module with
the following instruction.
• Multiple CPU transmission dedicated instruction
* 1: Refer to the manual of the Motion CPU for instructions dedicated to Motion.
* 2: For the multiple CPU transmission dedicated instruction, refer to the manuals of the Motion CPU,
C Controller module, and PC CPU module.
* 3: For the multiple CPU high-speed transmission dedicated instruction, refer to the following
manuals.
Writing/reading device data to/from the QCPU: QCPU (Q mode)/QnACPU Programming Manual
(Common Instructions)
Writing/reading device data to/from the Motion CPU: Manual of the Motion CPU
The Universal model QCPU(except Q02UCPU) allows executing the motion CPU
dedicated instruction several times in the same scan.
Since the motion CPU dedicated instruction can be executed consecutively to
different axis numbers, delay time of servo startup interval can be shortened.
*1
*2
*2
1.2 Features of multiple CPU system
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