Mitsubishi MELSEC-Q Series User Manual page 194

4
COMMUNICATIONS BETWEEN CPU MODULES
4
- 44 4.1 Communications between CPU modules using CPU shared memory
4.1.4 Communication using CPU shared memory by program
(b) Preventing separation for data exceeding 32 bits
1) Using user setting area
Programs are read from the start of user setting area.
With the write instruction, send data are written from the last address to the
start address of the user setting area.
Therefore, data separation can be avoided by creating an interlock device at
the start of data to be communicated.
An example for the program which interlocks CPU No.1 and CPU No.2 is
shown in Diagram 4.43.
Transmission side program (CPU No.1)
M0 M2
M2
FROM H3E1 H900 D10 K1
1)
M2 D0.0 D10.0
Set send data from D1 to D9.
M1
3)
SP.TO H3E0 H900 D0 K10 M3
M3
9)
M2 D0.0 D10.0 M1
11)
SP.TO H3E0 H900 D0 K1 M4
M4
1) CPU No.1 sets the send data from D1 to D9.
2) CPU No.1 turns on the send data setting complete flag (D0.0).
3) CPU No.1 writes the send data (D1 to D9) to the user setting area in CPU
No.1.
4) CPU No.2 reads the send data from the user setting area in CPU No.1.
5) CPU No.2 detects that the send data setting complete flag (D0.0) turns on.
6) CPU No.2 reads the receive data from D1 to D9.
7) CPU No.2 turns on the receive data processing complete flag (D10.0).
8) CPU No.2 writes the receive data processing complete flag to the user setting
area in CPU No.2.
9) CPU No.1 detects that the receive data processing complete flag (D10.0) turns
on.
10)CPU No.1 turns off the send data setting complete flag (D0.0).
11)CPU No.1 writes the send data setting complete flag to the user setting area in
CPU No.1.
12)CPU No.2 detects that the send data setting complete flag (D0.0) turns off.
13)CPU No.2 turns off the receive data processing complete flag (D10.0).
14)CPU No.2 writes the receive data processing complete flag to the user setting
area in CPU No.2.
Reception side program (CPU No.2)
M0
SET M2
5)
D0.0
2)
SET D0.0
SET M1
M2
12)
RST M1 D0.0
10)
RST D0.0
SET M1
M3
RST M2
RST M1
Diagram 4.43 Interlock program example
4)
FROM H3E0 H900 D0 K10
D10.0 6)
Operation using from D1 to D9
7)
M1
SET D10.0
8)
SP.TO H3E1 H900 D10 K1 M2
13)
D10.0 M1
RST D10.0
14)
SP.TO H3E1 H900 D10 K1 M3
M0: Read command
M1: S.TO in-execution flag
M2 M3: S.TO instruction completion device
SET M1
RST M1
SET M1
RST M1