Mitsubishi MELSEC-Q Series User Manual page 23

Generic Term/Abbreviation
SRAM card
Flash card
ATA card
Memory card
Motion module
GOT
Single CPU system
Multiple CPU system
CPU No.
CPU slot
Control CPU
Non-control CPU
Controlled module
Non-controlled module
(Non-group module)
Dedicated instruction
Generic term for Q2MEM-1MBS and Q2MEM-2MBS, Q3MEM-4MBS, and
Q3MEM-8MBS type SRAM card.
Generic term for Q2MEM-2MBF, and Q2MEM-4MBF type Flash card.
Generic term for Q2MEM-8MBA, Q2MEM-16MBA, and Q2MEM-32MBA type ATA card.
Generic term for SRAM card, Flash card and ATA card.
Generic term for Q172LX, Q172EX, Q173PX, Q172DLX, Q172DEX, and Q172DPX
modules dedicated to Mitsubishi motion controllers.
Generic term for Mitsubishi graphic operation terminal, GOT-A*** series and GOT-F***
series.
System in which a QCPU (including Q00JCPU) is installed in CPU slot for control.
System in which up to 4 CPUs can be installed to the main base unit for control.
Number assigned to the CPU modules in the multiple CPU system to distinguish each of
them.
CPU slot, slot 0, slot 1 and slot 2 are referred to as CPU No.1, No.2, No.3 and No.4
respectively.
Slot located next to and on the right of the power supply module in the main base unit.
CPU module that controls I/O modules, intelligent function modules mounted on the
main base unit or extension base units.
For example, when CPU No.2 controls a module installed in slot 3, CPU No.2 is the
control CPU for the module in slot 3.
QCPUs other than control CPUs.
For example, when CPU No.2 controls a module installed in slot 3, CPU No.1, 3 and 4
are non-control CPU for the module in slot 3.
I/O module or intelligent function module controlled by a control CPU.
For example, when CPU No.2 controls a module installed in slot 3, the module in slot 3
is a controlled module for CPU No.2.
I/O module or intelligent function module that is not a controlled module.
For example, when CPU No.2 controls a module installed in slot 3, the module in slot 3
is a non-controlled module for CPU No.1, 3 and 4.
Generic term for the multiple CPU transmission dedicated instruction and multiple CPU
high-speed transmission dedicated instruction
Description
A
- 21