Mitsubishi MELSEC-Q Series User Manual page 195

4
COMMUNICATIONS BETWEEN CPU MODULES
Transmission side program (CPU No.1)
Write
command
G10010.0
Remark
2) Using multiple CPU high speed transmission area
In the direct access mode, the data is transferred in order starting from the one
which was written to the user setting area first.
Using the device which is written after the data transfer regardless of kinds of
device or addresses can realize the data consistency of the transferred data.
Example for program executing interlock in CPUs No.1 and No.2 is shown in
Diagram 4.44.
U3E0\ U3E1\
M0 G10010.0 G10000.0
1)
Set the send data to the
user setting area
(U3E0\G10000
to G100009).
2)
SET G10010.0
6)
U3E0\ U3E1\
G10000.0
RST G10010.0
(1) CPU No.1 writes the send data to the user setting area.
(2) CPU No.1 writes that the data setting complete bit turns on to the user setting
area.
< Data in multiple CPU high speed transmission area of CPU No.1 are sent to
CPU No.2. >
(3) CPU No.2 detects the send data setting completion.
(4) CPU No.2 processes the receive data.
(5) CPU No.2 writes that the receive data processing completion turns on to the
user setting area.
< Data in multiple CPU high speed transmission area of CPU No.2 are sent to
CPU No.1. >
(6) CPU No.1 detects that the receive data processing completion turns on, and
turns off the data setting complete bit.
< Data in multiple CPU high speed transmission area of CPU No.1 are sent to
CPU No.2. >
(7) CPU No.1 detects that the send data setting completion turns off, and turns off
the receive data processing completion.
Diagram 4.44 Interlock program example
With an instruction such as the BMOV instruction, which writes 2 word or more
data to the user setting area, data are written from the last address to the start
address.
When writing the send data and interlock signal together with one instruction,
creating an interlock signal at the start of data will avoid data separation.
4.1 Communications between CPU modules using CPU shared memory
4.1.4 Communication using CPU shared memory by program
Reception side program (CPU No.2)
3)
U3E0\
G10010.0 G10000.0
U3E0\
7)
U3E0\
U3E0\ G10010.0 G10000.0
RST M0
U3E1\
4)
Operation using the
receive side data
5)
U3E1\
SET G10000.0
U3E1\
U3E1\
RST G10000.0
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