Configuring A Digital Data Block Using Ld 73 - Avaya Communication Server 1000 Installation And Commissioning Manual

Configure an E1/T1 card
Important:
The primary reference (PREF) must match the primary clock span number configured
through the Web interface.
You must configure a clock controller on each PRI Gateway containing digital trunks. Clock
references cannot be used between PRI Gateways.

Configuring a digital data block using LD 73

configuration required for a 1.5 Mb/s PRI data block including the clock controller and loop
alarm thresholds.
Configuring a digital data block using LD 73
1. Log on to the CS 1000E.
2. To access LD 73, enter:
3. Enter the responses shown in
92 Media Gateway 1000E PRI Gateway Installation and Commissioning
LD 73
73) on page 92.
Table 24: Digital data block configuration for PRI (LD 73)
Prompt Response
REQ aaa
TYPE DDB
MGCLK sl s c
- PREF Card
- SREF Card
MGCLK sl s c
- PREF Card
Comments? infodev@avaya.com
on page 92 describes the digital data block
Table 24: Digital data block configuration for PRI (LD
Description
Request (aaa = CHG, END, NEW, OUT, or PRT).
Digital data block.
Superloop, shelf, card number of PRI containing
the Primary Clock Reference.
The card number (1 to 8) should match the PRI
Gateway span number configured through the
Web interface.
Card number of PRI containing the primary clock
reference for the first IPMG.
Card number of PRI containing the Secondary
Clock Reference for the first IPMG.
To modify, use the CHG command (you can
change the PREF only if you change the
MGCLK).
Superloop, shelf, card number of PRI containing
the Primary Clock Reference for the second
IPMG.
The card number (1 to 8) should match the PRI
Gateway span number configured through the
Web interface.
Card number of PRI containing the Primary Clock
Reference for the second IPMG.
March 2013