Setting Up The Vivado Design Suite - Xilinx Virtex UltraScale FPGA VCU1287 Getting Started Manual

4. Select option (8) to configure the FPGA with the Quad 224 IBERT example design. Press
Enter and review the terminal for configuration progress:
Enter a Bitstream number (0-15):
8
Info: xilinx.sys opened
Info: Opening rev_1/set8/config.def
Info: Configuration definition file "rev_1/set8/config.def" opened
Info: Clock divider is set to 2
Info: Configuration clock frequency is 25MHz
Info: Bitfile "rev_1/set8/vu95Q224.bit" opened
...10%...20%...30%...40%...50%...60%...70%...80%...90%...100%
Configuration completed successfully

Setting Up the Vivado Design Suite

1. Connect the host computer to the VCU1287 board using the second standard-A plug to
micro-B plug USB cable. The standard-A plug connects to a USB port on the host
computer and the micro-B plug connects to J165, the Digilent USB JTAG configuration
port on the VCU1287 board
X-Ref Target - Figure 1-13
VCU1287 IBERT Getting Started Guide
UG1203 (v2016.4) December 15. 2016
Chapter 1: VCU1287 IBERT Getting Started Guide
(Figure 1-13).
Figure 1-13: JTAG Connector
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