Xilinx Virtex UltraScale FPGA VCU1287 Getting Started Manual page 9

All multi-gigabit transceiver (MGT) pins and reference clock pins are routed from the FPGA
to a connector pad that interfaces with Samtec Bulls Eye connectors.
connector pad.
X-Ref Target - Figure 1-2
The SuperClock-2 module provides LVDS clock outputs for the MGT transceiver reference
clocks in the IBERT demonstrations.
SMA connectors on the clock module which can be connected to the reference clock cables.
X-Ref Target - Figure 1-3
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
Note:
SuperClock-2 module.
For more information on the SuperClock-2 module, see the HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770)
VCU1287 IBERT Getting Started Guide
UG1203 (v2016.4) December 15. 2016
Figure 1-2 B shows the connector pinout.
Figure 1-2: A—MGT Connector Pad. B—MGT Connector Pinout
Figure 1-3
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
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Chapter 1: VCU1287 IBERT Getting Started Guide
shows the locations of the differential clock
[Ref 2].
Figure 1-2 A shows the
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