Xilinx Virtex UltraScale FPGA VCU1287 Getting Started Manual page 55

9. In the Clock Settings tab, select DIFF SSTL15 for the I/O Standard, enter AW14 for the
P Package Pin (the FPGA pins where the system clock is connected), and make sure the
Frequency (MHz) is set to 300
X-Ref Target - Figure 2-18
VCU1287 IBERT Getting Started Guide
UG1203 (v2016.4) December 15. 2016
(Figure 2-18).
Figure 2-18: Customize IP– Clock Settings
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Chapter 2: Creating the IBERT Cores
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