Simulating The Base Design Using Vivado Simulator - Xilinx KCU105 User Manual

4. In the Flow Navigator panel, click the Generate Bitstream option which runs synthesis,
implementation, and generates the bit file (see
be found under the following directory:
kcu105_control_plane/hardware/vivado/runs_user_extn/trd01.runs/
impl_1/
X-Ref Target - Figure 4-4

Simulating the Base Design Using Vivado Simulator

The targeted reference design can be simulated using the Vivado simulator. The testbench
and the Endpoint PCIe IP block are configured to use the PHY Interface for PCI Express
(PIPE) mode simulation.
The test bench initializes the bridge, does one double word (DW) write to BAR-mapped
address space, reads back from the same address, and compares the data with expected
pattern.
PCI Express Control Plane TRD
UG918 (v2017.2) July 18, 2017
Figure 4-4: User Extension Design—Generate Bitstream
www.xilinx.com
Chapter 4: Implementing and Simulating the Design
Figure 4-4). The generated bitstream can
UG918_c4_04_070717
32
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