Xilinx Virtex UltraScale FPGA VCU1287 Getting Started Manual page 30

Select an option
4. Select option (0) to configure the FPGA with the Quad 124 IBERT example design. Press
Enter and review the terminal for configuration progress.
Enter a Bitstream number (0-15):
0
Info : xilinx.sys opened
Info : Opening rev_1/set0/config.def
Info : Configuration definition file "rev_1/set0/config.def" opened
Info : Clock divider is set to 2
Info : Configuration clock frequency is 25MHz
Info : Bitfile "rev_1/set0/vu95Q124.bit" opened
...10%...20%...30%...40%...50%...60%...70%...80%...90%...100%
Configuration completed successfully
VCU1287 IBERT Getting Started Guide
UG1203 (v2016.4) December 15. 2016
Chapter 1: VCU1287 IBERT Getting Started Guide
www.xilinx.com
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