Chapter 3: Hardware Design - Xilinx Zynq UltraScale+ RFSoC ZCU208 User Manual

Hardware Design
The Vivado ® Design Suite project used to build this programmable logic (PL) design is located in
the install directory in the pl folder. The hardware design architecture is based on the RF
analyzer architecture (see Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide
(PG269)). Notable additions to this architecture include:
• MicroBlaze™ is replaced by the Cortex
• PL DDR4 support, including DMA, AXI4-Stream broadcaster and switch, and GPIO control
• Clocking scheme to support DDR4 and multi-tile synchronization
• I2C connection to control external clocks (CLK104, see ZCU208 Evaluation Board User Guide
(UG1410) and ZCU216 Evaluation Board User Guide (UG1390))
• Time division duplex (TDD) power up/down block to control the TDD real-time signal (RTS)
pins of ADCs and DACs
The following figure shows the high-level hardware architecture.
UG1433 (v1.2) October 27, 2021
RF Data Converter Evaluation Tool User Guide
-A53
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Chapter 3: Hardware Design

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