Control Registers - Panasonic MN101L Series User Manual

Chapter 2
CPU
2.2.3

Control Registers

The memory control register (MEMCTR) controls bus interface function.
Memory Control Register (MEMCTR: 0x03F01)
bp
Bit name
At reset
Access
bp Bit name
7-6
5
4 Reserved
3
2
1
0 MIESET
Always set the MEMCTR.IRWE to "0" except in writing xICR.IR by software.
The interrupt request may be cleared when operating the xICR by software while the MEM-
CTR.IRWE is "1". For example, when the bit operation to xICR is executed (the xICR is read,
..
modified, and overwritten by CPU), the interrupt request, which occurs during the above
read-to-write cycle is cleared because the IR is overwritten with "0" by software. To avoid
this, set the MEMCTR.IRWE to "0", which prevent the interrupt missing by software.
..
Setting the MEMCTR.MIESET to "1" disables all maskable interrupts after the PSW.MIE is
set to "0". If MEMCTR.MIESET is set to "1" when PSW.MIE is "1", the operation can not be
guaranteed.
..
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II - 16 Bus Interface
7 6
- - IVBM
0 0
R R
- Always read as 0.
Base address specification for interrupt vector table
IVBM 0: Interrupt vector base = 0x04000
1: Interrupt vector base = 0x00100
Must be set to 0.
- Always read as 0.
Software write set up for interrupt request bit
0: Even if data is written to each interrupt control register (xxxICR), the state of the
IRWE
interrupt request bit (xxxIR) will not change.
1: Software write enable
- Always read as 0.
Setting to allow multiple interrupts bit
0: After accepted an interrupt, MIE bit in PSW is set to "0".
1: After accepted an interrupt, MIE bit in PSW is set to "1".
5 4
Reserved
0 0
R/W R/W
Description
3 2
- IRWE
0 0
R R/W
1 0
- MIESET
0 1
R R/W