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Chapter 2 Basic CPU Functions
Be sure to use the MIE flag of
the PSW register to write to all
interrupt control registers.
By setting xxxLVn to '11' (level
3), the corresponding interrupt
vector
will
be
disabled,
regardless of the state of the
interrupt enable and interrupt
request flags.
34
Interrupts
2-4-3 Interrupt Control Registers
Interrupt control registers consist of the following: a non-maskable interrupt control
register (NMICR), external interrupt control registers (IRQnICR), and internal
interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR).
Non-maskable Interrupt Control Register (NMICR)
Non-maskable interrupt factors are stored in the non-maskable interrupt control
register (NMICR), and are used when a non-maskable interrupt is generated.
7
6
5
NMICR
Figure 2-4-2 Non-maskable Interrupt Control Register (NMICR: X'03FE1', R/W)
External Interrupt Control Registers (IRQnICR)
The external interrupt control registers (IRQnICR) control the interrupt level, valid
edge, and request/enable.
7
6
5
xxxLV1 xxxLV0 REDGn
IRQnICR
Figure 2-4-3 External Interrupt Control Register
(IRQnICR: X'03FE2' to X'03FE3', X'03FEB' to X'03FED', R/W)
4
3
2
1
0
WDIR
4
3
2
1
0
—
—
—
xxxIE
xxxIR
(at reset: ------0-)
WDIR
Watchdog interrupt request flag
0
No interrupt request
1
Happens interrupt request
(at reset: 000---00)
xxxIR
External interrupt request flag
0
No interrupt request
1
Happens interrupt request
xxxIE
External interrupt enable flag
0
Disable interrupt
1
Enable interrupt
REDGn
External interrupt valid edge flag
0
Falling edge
1
Rising edge
Interrupt level flag for external interrupt
xxxLV1
xxxLV0
The CPU has interrupt levels from 0 to 3.
This flag sets the interrupt level for interrupt requests.
n=0,1,2,3,4
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