Mulw 16-Bit X 16-Bit Multiplication (Signed - Panasonic MN101L Series User Manual

Chapter 2
CPU
2.4.3

MULW 16-bit x 16-bit multiplication (signed)

MULW (MOV 0x02, (0x03F07))
Operation
Bit Changes
VF: 0
NF: Set if the MSB of the result is "1", otherwise set to "0".
CF: 0
ZF: Set if the result is "0", otherwise set to "0".
Execution of 16-bit × 16-bit multiplication (signed)
1. Store the multiplier to DW0 register and the multiplicand to DW1 register.
2. Execute MOV 0x02, (0x03F07) (Extended calculation macro instruction MULW).
3. The value of the signed 16-bit of DW0 register is multiplied by the signed 16-bit of DW1 register. Then the
upper 16-bit of the results (32-bit) is stored in DW1 register and the lower 16-bit register is stored in DW0 reg-
ister.
This extended calculation instruction is generated by the compiler for MN101L series by
appointing an option (-mmuldivw).
.. ..
When this extended calculation instruction is executed, the handy address (HA) is updated in
"0x03F07"
.. ..
II - 22 Extended Calculation Instruction
DW0 * DW1 → {DW1, DW0}
Multiplies the signed 16-bit value of DW0 register by the signed 16-bit value of DW1
register, and store the upper 16-bit of the result (32-bit) in the DW1 register and the
lower 16-bit of the result in the DW0 register.
VF NF CF
0 0
Size, Cycles, Codes
6 nibbles
4 cycles
0000 0010 0111 0000 0010 0000
ZF