Pin Description - Panasonic MN101L Series User Manual

1.3.2

Pin Description

Input/
Pin name
Output
VDD30 -
VSS
VDD18 -
VDD11 -
VLC1 -
VLC2
VLC3
C1 -
C2
VREFP -
OSC1 Input
OSC2 Output
XI Input
XO Output
NRST Input
Output
DMOD Input
NATRON Input
The voltage level of VREFP must be over 0.8 V
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Table:1.3.1 Power Supply/Oscillation/Reset/Mode Pin
Power supply pin
Connect the capacitor of 1 µF or more between VDD30 and VSS.
Apply 0 V to VSS.
Internal power output pin
Connect the capacitor of 1 µF between VDD18 and VSS to stable V
Connect the bypass capacitor of 0.1 µF between VDD18 and VSS.
Internal power output pin (1.1 V)
Connect the capacitor of 1 µF or more between VDD11 and VSS.
LCD power supply pin
Supply the power under the following conditions.
(VDD30 ≤ VLC1 ≤ 3.6 V and 0 V ≤ VLC3 ≤ VLC2 ≤ VLC1)
Capacitors described in Chapter 17.3.4 must be connected in each pin.
When LCD function is not used, connect VLC1 to VDD30.
LCD voltage boost capacitor pin
When using the internal LCD booster circuit, connect the capacitor of 0.22 µF between C1 and C2.
ADC Reference power supply pin
When ADC is not used, connect VREFP to VDD30.
The voltage level of VREFP must be over 0.8 V
External high-speed oscillation pin
When the external high-speed oscillation is needed, connect the oscillator to the pins.
The external clock can be input through OSC1, and leave OSC2 open.
External low-speed oscillation pin
When the external low-speed oscillation is needed, connect the oscillator to the pins.
Reset pin (N-channel open drain pin)
When NRST is set to "Low", LSI is initialized. LSI reset condition is described in [2.5 Reset].
Mode setting pin
Always set DMOD to "Low" level, except for connecting the external LSI debugger or serial program-
mer.
Auto reset control pin
To use the auto reset function, set NATRON to "Low" level.
If not, set NATRON to "High" level.
Description
.
DD18
at any time including LSI power on.
DD30
at any time including LSI power on.
DD30
Chapter 1
Overview
Pin Description I - 15